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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是161-170 订阅

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NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array 19

NVSystolic: Heterogeneous Simulation Framework for Emerging ...

引用

19th International conference on Synthesis, Modeling, Analysis and Simulation Methods, and applications to Circuit Design, SMACD 2023

作者： Chithambara Moorthii, J. Khanv, Sufyan Suri, Manan Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)9798350332650

In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator. © 2023 IEEE.

关键词： Systolic arrays

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State of the Art on Stacked Intelligent Metasurfaces Communication, Sensing and computing in the Wave Domain 19

State of the Art on Stacked Intelligent Metasurfaces Communi...

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19th European conference on Antennas and Propagation, EuCAP 2025

作者： Di Renzo, Marco Université Paris-Saclay Cnrs CentraleSupélec Laboratoire des Signaux et Systémes Gif-sur-Yvette 91192 France King's College London Centre for Telecommunications Research Department of Engineering London WC2R 2LS United Kingdom

ISBN: (纸本)9788831299107

Stacked intelligent metasurface (SIM) is an emerging technology that capitalizes on reconfigurable metasurfaces for several applications in wireless communications. SIM is considered an enabler for integrating communication, sensing and computing in a unique platform. In this paper, we offer a survey on the state of the art of SIM for wireless communications. © 2025 European Association on Antennas and Propagation.

关键词： Dynamic metasurfaces reconfigurable intelligent surfaces stacked intelligent metasurfaces

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FPGA accelerated DeepSORT object tracking 24

FPGA accelerated DeepSORT object tracking

引用

24th International Carpathian Control conference, ICCC 2023

作者： Szanto, Peter Kiss, Tamas Sipos, Karoly Janos Budapest University of Technology and Economics Department of Measurement and Information Systems Budapest Hungary

ISBN: (纸本)9798350310221

Object detection and tracking is one of the most important vision algorithms in intelligent environments, applications based on it are the driving force behind the growing deployment of edge devices. As fpgas can implement application specific hardware accelerators, they not only offer outstanding performance but also increased energy efficiency which is a very important factor in edge devices and the most recent FPGA families include processing elements which greatly increase the efficiency and performance of AI inference. In this paper we present a heterogeneous FPGA based implementation of the popular DeepSORT tracking algorithm. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Dimensionality Reduction of Sparse Wireless Channel Based on Spatial Geometrical Structure of RIS Assisted Communication System 5

Dimensionality Reduction of Sparse Wireless Channel Based on...

引用

5th International conference on Inventive Research in computing applications, ICIRCA 2023

作者： Yadav Ch T, Krishna Teja Venkateswaran, K. Cmr Institute of Technology Department of Electronics & Communication Bengaluru India

ISBN: (纸本)9798350321425

reconfigurable Intelligent Surfaces (RIS) makes the channel more controllable by manipulating the propagation environment, so that wireless medium becomes smart when compared to conventional wireless communication system. In this study dataset from SPCUP 2021 is considered for a communication system involving two dimensional RIS consisting of NV reflecting elements vertically and NH elements horizontally each operating in binary state. When operating with fewer number of configurations the system becomes underdetermined which makes it difficult to estimate channel based on received signals. Hence it is required to reduce the dimension in the channel by finding the spatial geometry of RIS depending upon the similarities in the channel coefficients. Based on the simulations carried out in MATLAB it is concluded that square geometry (NV=NH)) is more preferable compared to rectangular geometry (NV\neq NH) since it exhibits periodicity in the channel coefficient. © 2023 IEEE.

关键词： Geometry

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Proceedings of the 12th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2022

Proceedings of the 12th International Symposium on Highly Ef...

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12th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2022

ISBN: (纸本)9781450396608

The proceedings contain 18 papers. The topics discussed include: performance evaluation on GPU-FPGA accelerated computing considering interconnections between accelerators;verifying hardware optimizations for efficient acceleration;accelerating decision tree ensemble with guided branch approximation;a hardware/software co-design approach to prototype 6G mobile applications inside the GNU radio SDR ecosystem using FPGA hardware accelerators;meta-programming design-flow patterns for automating reusable optimizations;a single-source C++20 HLS flow for function evaluation on FPGA and beyond;memory and energy efficient memory model and instruction set architectures for tree data structures;stream computation of 3D approximate convex hulls with an FPGA;and FPGA-dedicated network vs. server network for pipelined computing with multiple fpgas.

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Realization and characterization of HZO-based Schottky-Barrier FETs towards Logic-in-Memory applications 82

Realization and characterization of HZO-based Schottky-Barri...

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82nd Device Research conference, DRC 2024

作者： Nazzari, Daniele Wind, Lukas Mayr, Dominik Kim, Khiye Lellig, Sebastian Sistani, Masiar Weber, Walter M. Technische Universität Wien Institute of Solid State Electronics Gußhausstraße 25-25a Vienna1040 Austria Swiss Federal Laboratories for Materials Science and Technology Feuerwerkstrasse 39 Thun3602 Switzerland

ISBN: (纸本)9798350373738

The recent development of increasingly successful artificial intelligence applications have determined an unprecedented demand for optimized hardware for data-intensive computing. The currently employed device architecture, which relies on the separation between computing and memory units, requires frequent data transfers, causing energy inefficiencies and increased latency. A promising approach to solve this problem is represented by the Logic-in-Memory (LiM) architecture 1 , which aims at drastically reducing data transfer by relying on computing units that are also able to locally store information. A LiM enabling technology should be CMOS compatible and fully scalable. In recent years it was shown that, by recurring to an independently-gated Schottky-Barrier Field Effect Transistor (SB-FET), it is possible to obtain reconfigurable transistors that can show both n- and p-behavior without the need of doping2: while slightly increasing the complexity of the single transistor, this design allows to realize polymorphic logic gates with a reduced footprint with respect to the classic CMOS architecture3. When equipped with a memory element, such as a ferroelectric layer, this approach could prove promising for the realization of densely packed, adaptable LiM hardware. Here we explore the integration of a thin Hf0.5Zr0.5O2 (HZO) layer into a Double-Top-Gated (DTG) SB-FET, a device where two polarity gates (PG) are located onto the two Schottky Barriers. This design is explicitly chosen to obtain a ferroelectric layer just in proximity of the Schottky Barrier areas, as shown in Fig. 1a , by exploiting the property of HZO of crystallizing into such a phase only when in contact with specific metals, like Pd or TiN. This allows us to investigate how a ferroelectric HZO phase can influence the injection of carriers, without modifying the channel transport properties. HZO also offers the advantage of being ALD- and CMOS-compatible and has already been shown to be promising fo

关键词： Data transfer

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SCRA: Systolic-Friendly DNN Compression and reconfigurable Accelerator Co-Design 21

SCRA: Systolic-Friendly DNN Compression and Reconfigurable A...

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21st IEEE International Symposium on Parallel and Distributed Processing with applications, 13th IEEE International conference on Big Data and Cloud computing, 16th IEEE International conference on Social computing and Networking and 13th International conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Zhang, Xun Wang, ChengLiang Piao, Xingquan Ren, Ao Huang, Zhetong Chongqing University College of Computer Science Chongqing400044 China

ISBN: (纸本)9798350329223

Pruning has become an extremely powerful and effective technique to compress and accelerate sophisticated deep neural networks on resource-constrained platforms. Existing pruning and quantization methods aim to reduce parameter size and computation while maintaining accuracy. However, it is impractical to ignore hardware implementation when focusing on the accuracy of DNNs through pruning and quantization strategies. Moreover, a reduction in computational size does not necessarily result in an increase in inference *** order to strike a balance between DNN accuracy, inference efficiency, and hardware implementation, we propose SCRA, an efficient algorithm-architecture co-design that leverages stripe-based structured pruning strategy to reduce the data movement and fit the data flow of systolic arrays (SAs). Besides, considering the characteristics of the DSP48E2 in the FPGA, we present a quantization strategy for parallel computation of mixed-precision data, achieving acceleration of mixed-precision DNNs computation. Furthermore, we put forward an accelerator to fully exploit the benefits of the pruning strategy and parallel computation. Experimental results demonstrate that the proposed pruning strategy can achieve higher pruning rates without significant loss in model accuracy, and our accelerator achieves 4.79x speed up compared to the baseline. © 2023 IEEE.

关键词： Systolic arrays

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FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on fpgas

FlexPE: Flexible Processing Elements for Workload Optimizati...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Lasya Punya Sree Gundumogula Rachana Kaparthi Himanshu Rai Nanditha Rao International Institute of Information Technology Bangalore India

ISBN: (数字)9798350356830

ISBN: (纸本)9798350356847

Modern applications in the fields of machine learning, and scientific computing benefit from custom hardware configurations. In these cases, rather than designing or remapping the algorithms onto new accelerators, we propose flexible Processing Elements (PEs) that can adapt or reconfigure themselves according to the data type and compute type of the workloads. In this paper, we propose FlexPE, a framework that can generate reconfigurable and flexible (shrinkable or expandable) PEs according to the workload. It can generate an Field Programmable Gate Array (FPGA)-based custom accelerator in Register Transfer Language (RTL) with exactly the type of computations/data types required for the workload so that idle resources are not instantiated. FlexPE is evaluated on AMD-Xilinx ZedBoard and ZCU-104 fpgas on PolyBench and MachSuite workloads. Through this approach, we achieve a remarkable reduction of resources by nearly 35x on the fpgas. We achieve an impressive throughput increase of 81x and 43x on the two fpgas on average, and 35x reduction in resources compared to related work.

关键词： Machine learning algorithms Scientific computing Machine learning Logic gates Throughput Register transfer level Registers Field programmable gate arrays Optimization Hardware acceleration

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Observed Memory Bandwidth and Power Usage on FPGA Platforms with OneAPI and Vitis HLS: A Comparison with GPUs 38th

Observed Memory Bandwidth and Power Usage on FPGA Platform...

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38th International conference on High Performance computing, ISC High Performance 2023

作者： Siefert, Christopher M. Olivier, Stephen L. Voskuilen, Gwendolyn R. Young, Jeffrey S. Center for Computing Research Sandia National Laboratories AlbuquerqueNM87185 United States College of Computing Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)9783031408427

The two largest barriers to adoption of FPGA platforms for HPC applications are the difficulty of programming fpgas and the performance gap when compared to GPUs. To address the first barrier, new ecosystems like Intel oneAPI, and Xilinx Vitis HLS aim to improve programmability for FPGA platforms. From a performance aspect, fpgas trade off lower compute frequencies for more customized hardware acceleration and power efficiency when compared to GPUs. The performance for memory-bound applications on recent GPU platforms like NVIDIA’s H100 and AMD’s MI210 has also improved due to the inclusion of high-bandwidth memories (HBM), and newer FPGA platforms are also starting to include HBM in addition to traditional DRAM. To understand the current state-of-the-art and performance differences between fpgas and GPUs, we consider realized memory bandwidth for recent FPGA and GPU platforms. We utilize a custom STREAM benchmark to evaluate two Intel FPGA platforms, the Stratix 10 SX PAC and Bittware 520N-MX, two AMD/Xilinx FPGA platforms, the Alveo U250 and Alveo U280, as well as GPU platforms from NVIDIA and AMD. We also extract power measurements and estimate memory bandwidth per Watt ((GB/s)/W) on these platforms to evaluate how fpgas compare against GPU execution. While the GPUs far exceed the fpgas in raw performance, the HBM equipped fpgas demonstrate a competitive performance-power balance for larger data sizes that can be easily implemented with oneAPI and Vitis HLS kernels. These findings suggest a potential sweet spot for this emerging FPGA ecosystem to serve bandwidth limited applications in an energy-efficient fashion. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Field programmable gate arrays (FPGA)

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Tamper Proof reconfigurable Speech Encryption Engine 1

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2nd International conference on Intelligent computing Systems and applications, ICICSA 2023

作者： Vinoth Raj, R. Ashwin, M. Dineshwar, N. Thaneshwaran, R. Vijayakumar, M. Velammal Institute of Technology Panchetti Chennai India Government College of Engineering Dharmapuri India Electronics & Communication Engineering Saveetha Engineering College Chennai India

ISBN: (数字)9789819754120

ISBN: (纸本)9789819754113

In this paper, Rossler’s attractor and the circular shifting method are used to create a hardware-based encryption scheme that can be changed to protect speech communication. In order to ratify the limitations of software-based speech encryption schemes like low throughput, being prone to attacks, poor quality in the deciphered signal, an inadequate key space, and high computational overhead. An enhanced reconfigurable hardware-based speech encryption architecture based on a three-dimensional Rossler’s attractor that offers high randomness through highly sensitive initial conditions and control parameters. The keys for the diffusion process are generated by Rossler’s attractor, and by using circular shifting, the scrambling has been achieved. The proposed speech encryption scheme is validated by conducting various analyses, such as histogram and spectrogram analyses, correlation analyses, signal-to-noise ratio analyses, and key space analyses. The obtained results show that the chosen approach is extremely safe, offers peer-to-peer encryption, and works well for real-time speech communication. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Signal to noise ratio

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