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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是171-180 订阅

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Passive-Active Crosstalk Beyond Low-Frequency Breakdown in Mathematical-Physical Models of Liquid Crystal Phase Shifters at Low-Frequency applications

Passive-Active Crosstalk Beyond Low-Frequency Breakdown in M...

引用

International conference on Green Energy, computing and Intelligent technology 2024, GEn-CITy 2024

作者： Li, Jinfeng Li, Haorong Advanced Research Institute of Multidisciplinary Science Beijing Institute of Technology Beijing China School of Integrated Circuits and Electronics Beijing Institute of Technology Beijing China Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781837242689

While most of the liquid crystal-based configurable and reconfigurable devices nowadays were designed to operate at the high-frequency microwave, millimetre-wave and optical wavelengths, there is a scarce of discussion on their feasibility at transmitting the low-frequency (LF) spectrum (low-data-rate but featuring lower attenuation and longer-range communication or detection). This work identifies a crosstalk vulnerability between the LF transmission signal and the LC-driving bias field for the first time. Furthermore, we comparatively quantify diverse line length requirements spanning the spectrum from 1 Hz to 100 GHz for the same LC coaxial phase shifters but fabricated by two different strategies, one with the conventional alignment agent-rubbing process (technically demanding, time-consuming, and costly), the other one featuring rubbing-free at the cost of a reduced tuning range of permittivity per unit length (i.e., requesting a larger physical size for 360ι shifting to feed a phased array antenna). © The Institution of Engineering & technology 2024.

关键词： Crosstalk

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Phase-change materials-integrated MRR-type 2×2 optical switch based on slot-ridge waveguide structure 5

Phase-change materials-integrated MRR-type 2×2 optical swit...

引用

5th International Academic Exchange conference on Science and technology Innovation, IAECST 2023

作者： Shi, Nuo South China University of Technology School of Microelectronics Guangzhou China

ISBN: (纸本)9798350357738

All-optical computing has attracted attention for its faster computation speed and lower energy consumption compared to conventional electrical computing methods. Optical switches are the key basic units of optical computing devices. However, conventional optical switches suffer from the disadvantages of consuming external energy to maintain the switching state, high extinction ratio, and poor optical field modulation, which greatly limit the realization of large-scale photonic integrated circuits and optical pulse neural networks. In this paper, we utilize a Lumerical simulation platform to design a nonvolatile MRR-type 2 × 2 optical switch based on the phase-change materials Ge2Sb2Te5 (GST) using a slot-ridge waveguide, which possesses high extinction ratios of 25.31 dB at the THROUGH port and 8.97 dB at the DROP port. Changing the phase state of the GST modulates the transmission of the optical switch with a higher extinction ratio than previous optical switches. The absence of static power consumption in maintaining the phase state renders it very suitable for utilization in optical switch matrices and reconfigurable optical pulse neural networks, therefore presenting exciting prospects for these applications. © 2023 IEEE.

关键词： Optical switches

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FPGA-ENABLED HAND GESTURE RECOGNITION FOR SMART HOME applications

FPGA-ENABLED HAND GESTURE RECOGNITION FOR SMART HOME APPLICA...

引用

2025 International conference on Energy, Power, Environment, Control and computing, ICEPECC 2025

作者： Batool, Misbah Saleem, Mohsin Khan, Maryam N. Siddiqui, Faisal Salim, Ahmed Department of Electrical Engineering Namal University Mianwali Pakistan Software Development Cell Namal University Mianwali Pakistan Department of Electrical and Computer Engineering COMSATS University Islamabad Pakistan

ISBN: (纸本)9781837243235

Machine learning (ML) algorithms trained with hand gesture data have achieved accuracy rates close to 95%. However, despite this high accuracy, a trained ML algorithm requires hardware implementation to be effectively utilized in practical applications. In the proposed approach, we select one of the three investigated ML algorithms (CNN, ResNet50, and MobileNetV2) that demonstrates the best accuracy and make it compatible with loading onto a Field Programmable Gate Array (FPGA). This allows the algorithm to be effectively utilized in real-world applications. The optimized algorithm was implemented on a Zynq 7000 board to enhance performance, achieving greater efficiency, accuracy, and lower power consumption compared to traditional CPU-based or other architectures. The implementation was tested using a custom dataset containing six distinct hand gestures for detection and computation. Resource-efficient utilization led to a 2% increase in accuracy and a 5% reduction in processing time for the CNN-trained model on the FPGA compared to the CPU. Similarly, the ResNet50-trained model on the FPGA achieved 7% higher accuracy and 9% faster processing time compared to its execution on a CPU. Hand gesture recognition integrated with fpgas can achieve real-time responsiveness, energy efficiency, and reliability, making them ideal for resource-constrained environments that demand high performance. This demonstrates the FPGA's advantage in smart home solutions, which combine accuracy, speed, and low power consumption. © The Institution of Engineering & technology 2025.

关键词： Convolutional neural networks

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Implementation of intelligent robot target recognition technology based on FPGA development platform 4

Implementation of intelligent robot target recognition techn...

引用

4th International conference on Machine Learning and Computer Application, ICMLCA 2023

作者： Chen, Lin Ma, Xiao Ji, Xiang Tong, Lijuan He, Xiaoli School of Information Science Beijing Language and Culture University Beijing100000 China School of Management Capital Normal University Beijing100000 China

ISBN: (数字)9781510680265

ISBN: (纸本)9781510680258

Deep learning is currently a popular development in the field of artificial intelligence, which is based on the analysis of the process of input and processing information by the human brain, and the encoding and implementation of that process by a computer. There has been a tremendous development in deep learning for image and speech recognition, resulting in a number of related application technologies. fpgas (Field Programmable Logic Gate Arrays), as a semi-custom, reconfigurable hardware device, are increasingly used in the field of artificial intelligence. Intelligent robots, which combine information processing capabilities such as image, text, speech, position and motion, have very promising applications in industrial production and social life. In this paper, the correctness of the functionality of each functional module is confirmed through simulation, on-board verification schemes are designed and data results are statistically and analytically analysed, demonstrating the stability of the circuit system. The FPGA implementation based on the YOLOv3 algorithm was confirmed to be highly usable by connecting the development platform to an intelligent robot and conducting a comparative analysis. © 2024 SPIE.

关键词： Intelligent robots

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FPGA Architecture to Enhance Hardware Acceleration for Machine Learning applications 5

FPGA Architecture to Enhance Hardware Acceleration for Machi...

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5th International conference on computing Methodologies and Communication, ICCMC 2021

作者： Itagi, Anirudh Krishvadana, S. Bharath, K P Rajesh Kumar, M. Vellore Institute of Technology Alumni School of Electronics Engineering VelloreTN India Vellore Institute of Technology School of Electronics Engineering VelloreTN India

ISBN: (纸本)9781665403603

Many algorithms have been developed in the field of Machine learning and its sub-fields such as neural networks, Deep learning and so on, for applications such as pattern classification, image and video processing, statistical data mining and so forth. These algorithms perform such tasks with remarkable accuracy. However, when implemented in traditional processor core software, many of these algorithms get choked when the size of the network or computational demand of the algorithm scales up. fpgas and ASICs offer higher computation capability, throughput and bandwidth. Features such as massive parallel processing, high performance and reliability, are strong arguments for fpgas for Deep Neural Network applications. fpgas offer reconfigurable, flexible architectures where even the most popular GPUs fall short. This paper proposes a robust, re-configurable architecture for deploying Machine learning algorithms and presents its advantages by implementing a Neural Network in an FPGA and comparing its results with an implementation in a Raspberry Pi. © 2021 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Obstacle Avoidance: Transfer Learning and FPGA for Acceleration

Obstacle Avoidance: Transfer Learning and FPGA for Accelerat...

引用

Mobile computing and Sustainable Informatics (ICMCSI), International conference on

作者： Jeyalakshmi. V Arjun Chakkrapani Preethaa Jansirani Kripa. S Vaithiyanathan. D Department of Electronics and Communication Engineering College of Engineering Guindy Chennai Tamil Nadu India Department of Electronics and Communication Engineering NIT Delhi India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

Obstacle detection and avoidance have historically been manual processes. With the advent of neural networks, many processing tasks have been made autonomous with more efficient by obtaining a wide variety of data from their surroundings to perform the next move. Training these networks is computationally intensive, which became the driving force behind transfer learning. Field Programmable Gate Arrays (fpgas) which revolutionized reconfigurable logic is the next choice considered the opportunity to interleave the processing tasks between a general-purpose processor and dedicated logic blocks. Extending this concept to collision detection and using hardware acceleration to speed up the decision process can be highly beneficial, especially in such time critical applications. In this article, the idea above has been reviewed, and a method to implement the system has been proposed.

关键词： Training Neural networks Transfer learning Speech recognition reconfigurable logic Logic gates Throughput Collision avoidance Field programmable gate arrays Python

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Performance Modeling and Scalability Analysis of Stream computing in ESSPER FPGA Clusters

Performance Modeling and Scalability Analysis of Stream Comp...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Ryota Miyagi Ryota Yasudo Kentaro Sano Hideki Takase The University of Tokyo Tokyo Japan Kyoto University Kyoto Japan RIKEN Kobe Japan

ESSPER is a flexible and scalable FPGA cluster system designed for reconfigurable HPC, with customizability, scalability, and interoperability with existing HPC systems. The inherent characteristics of ESSPER make it a superior alternative for achieving highly scalable computing solutions, particularly for compute-intensive applications such as numerical simulations and machine learning. However, constraints in communication bandwidth or latency can impact performance and scalability. This paper builds upon a previous performance model study to analyze performance modeling and scalability of streaming computation using a 1D ring of cascaded fpgas with high-speed, low-latency communication links in ESSPER. For evaluation and verification, we implemented a simple vector addition on ESSPER. The Result indicates that measured performance metrics closely align with predictions from the performance model. This model can also be used to estimate performance for other ESSPER applications.

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DESIGN TRANSFORMATION CARDS FOR reconfigurable ROBOTICS: CASE STUDY OF AN EXPANDABLE ROBOT FOR CLEANING TASKS

DESIGN TRANSFORMATION CARDS FOR RECONFIGURABLE ROBOTICS: CAS...

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ASME International Design Engineering Technical conferences / 42nd Annual Computers and Information in Engineering conference (IDETC-CIE) / 35th International conference on Design Theory and Methodology (DTM)

作者： Kalimuthu, M. Hayat, A. A. Pathmakumar, T. Prabakaran, V. Elara, M. R. Wood, K. L. Singapore Univ Technol & Design Engn Prod Dev 8 Somapah Rd Singapore 487372 Singapore Univ Colorado Denver Coll Engn Design & Comp 1200 Larimer StSte 3034 Denver CO 80204 USA

ISBN: (纸本)9780791887349

reconfigurable robotic systems (RRS) have demonstrated their usefulness in various sectors, including surveillance, rescue missions, space exploration, maintenance, and cleaning. However, designing adaptable and flexible robotic systems is challenging, and researchers have developed innovative mechanical designs that can optimize the performance of these systems in different applications. This paper introduces a method for designing a reconfigurable robot using earlier proposed design transformation cards (DTC) that illustrate mechanical mechanisms based on the transformation design theory. These cards serve as a visual tool for ideation and design-by-analogy, enabling designers to explore the best possible combinations of mechanical mechanisms for their robot design. The case study application of the DTC is presented by designing the block of an expandable Tetris-inspired robot named e-Smorphi (expandableSmorphi) which consists of four units of expandable blocks that can change their dimensions in length and width, allowing for adaptation to different environments in two dimensions. The proposed design has potential application to the cleaning and maintenance industry, where the objective is to be maximizing the area coverage. The paper also describes experiments with the selected prototype, highlighting the reconfiguration in two dimensions while accessing the environment for cleaning and maintenance (CnM) tasks. The limitations and advantages of using DTC are also discussed as insights into the development of new design tools and techniques for reconfigurable robotics, paving the way for further innovation and advancements in the field.

关键词： Robotics Surveillance Dimensions Design Design theory Innovation Engineering prototypes Maintenance Robots

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Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper)

Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay ...

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International conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Mohamed Bouaziz Suhaib A. Fahmy King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

Coarse-grained reconfigurable arrays (CGRAs) are reconfigurable architectures that combine the efficiency of custom datapaths with the flexibility of fpgas. Optimized word-level functional units with reconfigurable interconnect enable a wide range of applications. Due to the irregular data movement patterns and the diversity of real-world HPC applications, a traditional homogeneous regular-shaped CGRA architecture can be sub-optimal. A more application-specific arrangement of resources could, however, result in poor hardware reuse and increased deployment effort for a CGRA. Using CGRA overlays can increase hardware reuse while maintaining high performance of a more optimized architecture. This proposal uses and builds upon the built-in tools of the MLIR infrastructure to target a class of applications that can be analyzed, rewritten, and optimized based on the available resources of an underlying CGRA architecture, thereby better exploiting hardware resources.

关键词： Program processors Systems architecture Hardware reconfigurable architectures Proposals Arrays Field programmable gate arrays

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Towards Hardware Support for FPGA Resource Elasticity 25

Towards Hardware Support for FPGA Resource Elasticity

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25th Euromicro conference on Digital System Design (DSD)

作者： Awan, Ahsan Javed Aliyeva, Fidan

ISBN: (纸本)9781665474047

fpgas are increasingly being deployed in the cloud to accelerate diverse applications. They are to be shared among multiple tenants to improve the total cost of ownership. Partial reconfiguration technology enables multitenancy on FPGA by partitioning it into regions, each hosting a specific application's accelerator. However, the region's size can not be changed once they are defined, resulting in the underutilization of FPGA resources. This paper argues to divide the acceleration requirements of an application into multiple small computation modules. The devised FPGA shell can reconfigure the available PR regions with those modules and enable them to communicate with each other over Crossbar interconnect with the Wishbone bus interface. The implemented crossbar's reconfiguration ability allows to modify the number of allocated modules and allocated bandwidth to those modules while preventing any invalid communication request. The envisioned resource manager can increase or decrease the number of PR regions allocated to an application based on its acceleration requirements and PR regions' availability.

关键词： Cloud computing Crossbar fpgas Partial Reconfiguration Resource Elasticity

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