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1st International conference on Electronics, Communication and Signal Processing, ICECSP 2024

作者： Muralidhar, Pullakandam Reddy, Yanamala Rama Muni Varsha, Potluri Satya Sri Sharanya, Vattam Sai Prasanthi, Chekka Leela National Institute of Technology Department of Electronics and Communication Engineering Warangal India

ISBN: (纸本)9798350364590

LSTM, a recurrent neural network (RNN) well-suited for sequential data tasks, often incurs computational expenses during training and deployment, particularly with large and intricate models. The enhancement of LSTM network performance can be accomplished through hardware acceleration. Field-programmable gate arrays (fpgas), enabling custom circuit implementation, can facilitate the creation of hardware accelerators for LSTM networks, resulting in substantial speed improvements over software implementations. An LSTM network hardware accelerator was implemented on the ZedBoard, a well-known FPGA development board. Performance evaluations of this accelerator across various time series datasets were conducted. The results demonstrated that the proposed accelerator achieved speedups of up to 45x compared to the software implementation. The accelerator's performance is on par with leading LSTM accelerators implemented on other FPGA platforms. The accelerator attains a performance level of 1.203 GOP/S while operating within a power consumption of 0.235W, making it well-suited for power-constrained applications. © 2024 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Design a hexagonal shape frequency reconfigurable antenna for new C-band 5G applications

Design a hexagonal shape frequency reconfigurable antenna fo...

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2022 IEEE International conference on Electronics, computing and Communication Technologies, CONECCT 2022

作者： Ganesh, M. Raghava, N.S. Sabapathy, T. Delhi Technological University Dept. of Ece Delhi110042 India Universiti Malaysia Perlis Advanced Communication Engineering Faculty of Electronic Engineering Technology Paugh Putra 02600 Malaysia

ISBN: (数字)9781665497817

ISBN: (纸本)9781665497817

In this Communication, a simple hexagonal shape frequency reconfigurable antenna is designed with reduced ground plane for new C-band 5G (3.7GHz-3.98GHz applications. To enable frequency reconfiguration a PIN diode is adopted in the reduced ground plane with a gap size of 1mm. When diode is in OFF state the designed antenna resonates at 3.6 GHz with a bandwidth of 760 MHz, range used for Wi-Max and in ON state the designed structure resonates at 3.8 GHz with a bandwidth of 930 MHz, range used for New C-band 5G networks. The designed structure of an antenna is etched on a Fr-4 substrate with a size of 38X36X1.6mm3. © 2022 IEEE.

关键词： Microstrip antennas

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FPGA-based Accelerator for FFT-Processing in Edge computing

FPGA-based Accelerator for FFT-Processing in Edge Computing

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IEEE International Workshop on Intelligent Data Acquisition and Advanced computing Systems: technology and applications

作者： Peter Schulz Grigore Sleahtitchi HAW Hamburg Hamburg

Edge computing bridges the gap between end devices on the Internet of Things (IoT) and central, server-based IT services by accelerating tasks which otherwise could not be executed on the IoT device itself. The Fast Fourier Transformation (FFT) is used as an example for the arithmetic tasks to be supported. To support such specific applications, we envisage a concept for edge computing in which co-processing is implemented using Field Programmable Gate Arrays (fpgas). This article first describes certain edge computing requirements using the example of moving drones. This involves the case-by-case reconfiguration of the computation hardware and a handover mechanism from one edge node to another. Then follows the description of an FPGA-based FFT accelerator unit and its extension to an FFT co-processor. The development took place under the proviso that, for example, drones can request different co-processors and that the drones can also change the edge node when changing a radio cell, which results in a handover of the co-processor context. Regarding the FPGA part this means that the co-processor is part of a partially reconfigurable environment, and the co-processor must support the handover mechanisms in terms of hardware. Finally, the need for FPGA resources is analyzed, also in comparison with alternative solutions.

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Fpga-based reconfigurable architectures for dsp computations 1st

Fpga-based reconfigurable architectures for dsp computations

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1st International conference on Frontiers in Smart Systems Technologies, ICFSST 2019

作者： Mazher Iqbal, J.L. Manikandan, T. Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology Avadi Chennai India Rajalakshmi Engineering College Chennai India

ISBN: (纸本)9789811550287

With extensive usage of Field Programmable Gate Arrays (fpgas), a reconfigurable computing platform enhances the wide variety of Digital Signal Processing (DSP) applications using Lookup Table (LUT), Flip-Flop, and multiplexers. reconfigurable computation using memory becomes a subject of current research. fpgas can be reprogrammed an unlimited number of times in which various DSP algorithms can be executed on a single hardware device, just as many different software algorithms can run on a conventional processor. The general architectures for DSP consist of a reconfigurable interconnection, Computational Elements (CEs), and memory. This article discusses on the CE architectures based on Memory (CEMs) and Serial arithmetic (CESs). reconfigurable computing based on memory is much faster, reliable, and, hence the computation using memory requires less delay and power. The CEMs perform multiplication and addition using LUT and the CESs perform computation using serial arithmetic’s. The results of the CESs, CEMs, and the computational reuse processing elements are compared. The architectures design based on CEMs significantly improves the performance of the previously reported results in terms of speed, area, and power using Xilinx Virtex-II FPGA, and Xilinx Vivado software. © Springer Nature Singapore Pte Ltd 2021.

关键词： Digital signal processing

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Design and analysis of a Foldable Miniaturized Single Band Origami Antenna for Space applications 9

Design and analysis of a Foldable Miniaturized Single Band O...

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9th International conference on Advanced computing and Communication Systems, ICACCS 2023

作者： Aldrin Antony, A. Shamith, M. Infant Baiju, J. Ezhil, P. Neebha, T. Mary Andrushia, A. Diana Karunya Institute of Technology and Sciences Karunya Nagar Department of Electronics and Communication Engineering Coimbatore India

ISBN: (纸本)9798350397376

Next-generation systems in airborne, spaceborne, and terrestrial applications are expected to greatly rely on deployable reconfigurable high-performance antenna systems. This research paper introduces a novel design concept for an origami antenna that is both foldable and physically reconfigurable. The antenna is optimized for use in the 2.45 GHz industrial, scientific, and medical (ISM) band, making it suitable for a range of industrial, scientific, and medical applications. The antenna is modeled and analyzed using the finite element method-based Ansys Electronics Desktop. To be deployed for foldable and conformal applications, the antenna is designed on the magic cube made of flexible material (Kapton polyimide) with ?r = 3.5, loss tangent = 0.002, and patch thickness of 0.12 mm. The radiator is designed on the folded magic cube resulted in a miniaturized volume of 30 × 30 × 30 mm3. The origami-based antenna proposed in this study boasts several key features, including compact size, flexibility, foldability, wide bandwidth, bi-directional radiation pattern, and a high gain value of 2.7 dBi. These unique features position the proposed antenna as a strong candidate for use in various applications such as space exploration, medical settings, military operations, and rescue missions. © 2023 IEEE.

关键词： Finite element method

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Accelerated Spiking Convolutional Neural Networks for Scalable Population Genomics 14

Accelerated Spiking Convolutional Neural Networks for Scalab...

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14th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2024

作者： Corradi, Federico Shen, Zhanbo Zhao, Hanqing Alachiotis, Nikolaos Eindhoven University of Technology Netherlands University of Twente Enschede Netherlands

ISBN: (纸本)9798400717277

Population genomics studies the genetic composition of populations to explain the evolutionary mechanisms that have contributed to species' adaptation to their environment. With continuous advances in DNA sequencing technologies, dataset sizes have grown, leading to an increased demand for processing power. Typical acceleration efforts for bioinformatics map established analytical models, including Convolutional Neural Networks (CNNs), to accelerator hardware like Graphical Processing Units (GPUs) and Field-Programmable Gate Arrays (fpgas). However, these methods are not explicitly designed for high throughput or efficient mapping to these platforms, limiting their performance potential. Here, we address two major computational problems in population genomics: detecting selective sweeps and recombination hotspots. These evolutionary processes, crucial for species adaptation and survival, find applications in plant breeding, human genetics, and drug design. We propose a scalable solution that anticipates larger sample sizes, and, for the first time, we introduce a co-design approach that explores SCNNs for scalable population genomics and their implementation on FPGA technology. We choose SCNNs because these can be efficiently implemented on FPGA hardware due to their massive parallelism and binary communication, resulting in lower resource utilization and high-Throughput performance. Our findings show that when using SCNNs, it is only necessary to process a portion of the sample size while maintaining a classification accuracy comparable to conventional CNNs. We demonstrate the performance of our system in FPGA hardware for several genomic tasks, achieving up to 3X throughput and 100X less power consumption. This paves the way for a high-performance, future-proof acceleration solution that addresses the computational challenges of increasing sample sizes and longer chromosome lengths. © 2024 Owner/Author.

关键词： Genome

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FPGA-Based Near-Memory Acceleration of Modern Data-Intensive applications

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IEEE MICRO 2021年第4期41卷 39-48页

作者： Singh, Gagandeep Alser, Mohammed Cali, Damla Senol Diamantopoulos, Dionysios Gomez-Luna, Juan Corporaal, Henk Mutlu, Onur Swiss Fed Inst Technol CH-8092 Zurich Switzerland Carnegie Mellon Univ Pittsburgh PA 15213 USA IBM Res Europe Zurich Lab CH-8803 Ruschlikon Switzerland Eindhoven Univ Technol NL-5612 Eindhoven Netherlands

Modern data-intensive applications demand high computational capabilities with strict power constraints. Unfortunately, such applications suffer from a significant waste of both execution cycles and energy in current computing systems due to the costly data movement between the computation units and the memory units. Genome analysis and weather prediction are two examples of such applications. Recent field-programmable gate arrays (fpgas) couple a reconfigurable fabric with high-bandwidth memory (HBM) to enable more efficient data movement and improve overall performance and energy efficiency. This trend is an example of a paradigm shift to near-memory computing. We leverage such an FPGA with HBM for improving the prealignment filtering step of genome analysis and representative kernels from a weather prediction model. Our evaluation demonstrates large speedups and energy savings over a high-end IBM POWER9 system and a conventional FPGA board with DDR4 memory. We conclude that FPGA-based near-memory computing has the potential to alleviate the data movement bottleneck for modern data-intensive applications.

关键词： DRAM Chips Energy Conservation Field Programmable Gate Arrays Genomics Low Power Electronics Weather Forecasting FPGA Based Near Memory Acceleration Data Intensive applications High Computational Capabilities computing Systems Computation Units Memory Units Genome Analysis High Bandwidth Memory High End IBM POWER 9 System FPGA Based Near Memory computing Data Movement Bottleneck Field Programmable Gate Arrays Weather Prediction Prealignment Filtering Step Energy Efficiency Energy Savings Field Programmable Gate Arrays Genomics Bioinformatics Random Access Memory Computational Complexity Instruction Sets Table Lookup

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Architecture of IoT-Based Collaborative Laboratory for reconfigurable SoC: Review and Development

Architecture of IoT-Based Collaborative Laboratory for Recon...

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Education conference (GeCon), IEEE German

作者： Rashed Al Amin Veit Wiese Mohammad Musfiqur Rahman Sven Jacobs Steffen Jaschke Roman Obermaisser Institute for Embedded Systems University of Siegen Siegen Germany Computer Science Education University of Siegen Siegen Germany

reconfigurable System-on-Chip (SoC) is a computing architecture that allows users to program and reprogram the hardware to perform different tasks, making it highly flexible and adaptable. Due to its potential to significantly accelerate various applications, reconfigurable SoC has become a subject of much research for academicians and industry. On the other hand, the classical practice of experimenting in the laboratory has been changing radically with the advanced utilization of computers, electronic devices, and the internet. As a result, it has given birth to a new concept of laboratory practice called Internet-of-Things (IoT) based collaborative simulation laboratory, which enables students to access and use the laboratory equipment at their convenience, enabling them to learn at their own pace and comfort. First, this paper reviewed the state of the art of reconfigurable SoC, specially Field-Programmable Gate Arrays (fpgas) laboratory architecture. Then, it developed an IoT-based collaborative simulation laboratory for reconfigurable SoC, allowing multiple students to work together to solve laboratory tasks remotely. Furthermore, this laboratory architecture is for reconfigurable fpgas, which can manage several tasks automatically, such as logic synthesis, logic simulation, and FPGA run from multiple fpgas or SoC. In addition to its benefits, the capability to virtualize user input/output interfaces and remotely measure the design's response further enhances its advantages. However, this proposed laboratory architecture is essential not only for doing laboratory tasks remotely but also simplifies the existing teaching methods and helping evaluate student performance in the examination.

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A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters 32

A Flexible Real-Time Stereo Vision Architecture for Multiple...

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32nd International conference on Field-Programmable Logic and applications (FPL)

作者： Meng, Zhaoteng Shu, Lin Hao, Jie Chinese Acad Sci Inst Automat Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Guangdong Inst Artificial Intelligence & Adv Comp Guangzhou Peoples R China

ISBN: (纸本)9781665473903

It is significant for a stereo vision real-time computing system to flexibly adapt to different parameters of stereo matching without re-customizing hardwares. In this paper, a configurable pipelined hardware architecture based on the sum of absolute differences (SAD) algorithm is proposed. We split the SAD calculation into two parts to accommodate pipelined computing. The architecture can be configured with different resolutions, window sizes, and disparity levels without stopping and restarting. In addition, it can be configured as a multiple-data-stream mode and we have developed a configuration generation algorithm for the mode. The presented architecture is synthesized and implemented on a Xilinx ZCU104 board. The evaluation results demonstrate that the real-time computing of 480P, 720P, and 1080P video streams can be process at 250MHz with the peak computing performance of 480P/784fps at the disparity level of 125. It uses 60% LUTs, 34% registers, and 39% BRAM, producing flexible configurability and superior computing performance than the other similar work.

关键词： stereo vision stereo matching real-time reconfigurable architecture SAD FPGA multiple-data-stream

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reconfigurable Hardware Implementation of CNN Accelerator using Zero-bypass Multiplier 6

Reconfigurable Hardware Implementation of CNN Accelerator us...

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6th International conference on Electronics, Communication and Aerospace technology, ICECA 2022

作者： Vanitha, M. Ganesh, Guntamadugu Thirumalesh, G. Tharun, E. Saveetha Engineering College Dept. of Ece Chennai India

ISBN: (纸本)9781665482714

Convolutional Neural Networks (CNNs) have undergone accelerated growth due to their capacity to resolve challenging image recognition problems. They are utilized to handle an increasing number of difficulties, such as speech recognition, and the segmentation and categorization of images. The ever-increasing processing needs of CNNs are spawning the market for hardware support strategies. Moreover, CNN workloads are of a streaming nature, which makes them a good choice for reconfigurable hardware architectures like as Field Programmable Gate Arrays (fpgas). Neural networks are a sort of computer architecture inspired by the way the human brain processes information. A artificial neural network consists of a large number of densely interconnected individual processors, or neurons. By adding a simplified bypass zero multiplier to the neural computing of the system, the proposed system may reduce the processing time and complexity while handling a broad range of datasets. The suggested CNN comprises of two hidden layers and two convolutional layers. The proposed CNN is implemented on a Xilinx zynq 7z020 FPGA using the verilog HDL programming language, with the consideration for space utilization, power estimation, and logical utilization. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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