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33rd International conference on Field-Programmable Logic and applications (FPL)

作者： Mazraeli, Mohammadmahdi Gao, Yu Chow, Paul Univ Toronto Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9798350341515

With the deployment of fpgas in a data center, there is the opportunity to build large multi-FPGA applications. In this paper, we design a partitioner to address the problem of efficiently assigning the various tasks of a large multi-FPGA application to individual network-connected fpgas according to constraints that consider resource usage, communication bandwidth and communication latency. By using simulated annealing, we can modify the cost function as new objectives and constraints are determined. We build on the Galapagos multi-FPGA platform by introducing a multi-die shell to extend Galapagos to more recent FPGA boards and design the partitioner to work on any collection of single- and multi-die fpgas. Finally, We evaluate the new shell and partitioner using micro-benchmarks and analyze the partitioning of a real-world multi-FPGA application, a Transformer model.

关键词： FPGA reconfigurable computing Partitioning

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly applications on fpgas

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2022年第2期15卷 1–33页

作者： Asiatici, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci EPFL IC IINFCOM LAP INF 137Batiment INFStn 14 CH-1015 Lausanne Switzerland

applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on fpgas due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24x area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

关键词： High performance computing reconfigurable computing nonblocking caches DRAM cuckoo hashing irregular memory accesses

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Towards Efficient and reconfigurable Neuromorphic computing using an Embedded FPGA in 22nmFDX 22

Towards Efficient and Reconfigurable Neuromorphic Computing ...

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22nd IEEE Interregional NEWCAS conference (NEWCAS)

作者： Ghonem, Ahmed Zaky Elewa, Sherif Maher Tawfik, Eslam Yahya Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9798350361766;9798350361759

There is a rising demand for AI workloads running on the edge that are increasingly complex, calling for more efficient computing platforms. Neuromorphic computing is a class of electronic circuits that aim to mimic a biological brain's functionality and computational efficiency. Its applications scale from low-duty cycles high-performance tasks to high-duty cycle ultra-low power operations. Embedded fpgas (efpgas) can address these demands given their flexibility compared to ASIC, low latency, and lower energy consumption compared to CPUs. efpgas provide adaptive performance and enable prototyping and deployment of new designs post-silicon manufacturing. In this work, we aim to combine the reconfigurability of the eFPGA with the efficiency of digital neuromorphic circuits to provide efficient and flexible hardware solutions for AI workloads. We evaluate primitives found in a typical neuromorphic computing system, such as rate coding, Izhikevich (IZH) neuron model, and spike-time-dependent-plasticity (STDP) learning rule on an eFPGA fabricated in 22nmFDX. We report the power and utilization of these primitives and propose architectural improvements to the eFPGA to better implement a complete and reconfigurable neuromorphic processor for various AI workloads.

关键词： Embedded FPGA Izhikevich Neuron model Leaky-Integrate-and-Fire Online-Learning Rate Encoding reconfigurable computing Spiking Neural Networks STDP

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AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded applications 10

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded A...

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10th Nordic Circuits and Systems conference

作者： Othman, Ahmad Kamaleldin, Ahmed Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9798331517663;9798331517670

The rapid expansion of the Internet of Things, wireless sensor networks, and robotics applications have established embedded systems as a fundamental component of modern computing. Despite this growth, optimizing power consumption and computing resources remains critical. Traditional embedded platforms often struggle with fixed hardware configurations that limit their adaptability and efficiency. To address these issues, this paper presents a novel adaptive processor architecture based on RISC-V ISA which introduces reconfigurable execution regions capable of supporting mixed-precision operations (16/8/4-bit). These reconfigurable execution regions execute and continuously adapt to varying precision and operational demands triggered by custom RISC-V instructions that activate the desired region at specific precision levels. The reconfiguration process is managed through dynamic function exchange (DFX) targeting AMD/Xilinx XCZU7EV FPGA device. The evaluation demonstrates that the modified core efficiently utilizes FPGA resources, with 6,396 LUTs and 2,679 FFs allocated, and operates with a dynamic power consumption of 24 mW at 50 MHz. The reconfiguration time is 76 ms for each reconfiguration execution region, incorporating the overhead required for reconfiguration management and control. These results highlight the core's potential to allow the realization of RISC-V-based reconfigurable cores without degrading performance and energy efficiency for embedded applications.

关键词： Embedded Systems RISC-V Processor Architecture Dynamic Function Exchange fpgas

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reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach 20th

Reconfigurable Edge Hardware for Intelligent IDS: Systematic...

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20th International Symposium on Applied reconfigurable computing (ARC)

作者： Foudhaili, Wadid Nechi, Anouar Thermann, Celine Al Johmani, Mohammad Buchty, Rainer Berekovic, Mladen Mulhem, Saleh Univ Lubeck Inst Comp Engn ITI Lubeck Germany

ISBN: (纸本)9783031556722;9783031556739

Intrusion detection systems (IDS) are crucial security measures nowadays to enforce network security. Their task is to detect anomalies in network communication and identify, if not thwart, possibly malicious behavior. Recently, machine learning has been deployed to construct intelligent IDS. This approach, however, is quite challenging particularly in distributed, highly dynamic, yet resource-constrained systems like Edge setups. In this paper, we tackle this issue from multiple angles by analyzing the concept of intelligent IDS (I-IDS) while addressing the specific requirements of Edge devices with a special focus on reconfigurability. Then, we introduce a systematic approach to constructing the I-IDS on reconfigurable Edge hardware. For this, we implemented our proposed IDS on state-of-the-art Field Programmable Gate Arrays (fpgas) technology as (1) a purely FPGA-based dataflow processor (DFP) and (2) a co-designed approach featuring RISC-V soft-core as FPGA-based soft-core processor (SCP). We complete our paper with a comparison of the state of the art (SoA) in this domain. The results show that DFP and SCP are both suitable for Edge applications from hardware resource and energy efficiency perspectives. Our proposed DFP solution clearly outperforms the SoA and demonstrates that required high performance can be achieved without prohibitively high hardware costs. This makes our proposed DFP suitable for Edge-based high-speed applications like modern communication technology.

关键词： Intrusion detection system Reconfigurabile Hardware Edge Device FPGA-based RISC-V Soft-Core

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A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET 67

A Novel Delay-Aware Packing Algorithm for FPGA Architecture ...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Lu, Sheng Shang, Liuting Jung, Sungyong Zhang, Yichen Pan, Chenyun Univ Texas Arlington Dept Elect Engn Arlington TX 76019 USA

ISBN: (纸本)9798350387186;9798350387179

reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to traditional CMOS technology. In this paper, we develop a more efficient 2-input look-up table (LUT) based on the reconfigurable field-effect transistors (RFETs), leading to a smaller transistor usage and a smaller critical path delay. The cells are organized into regular matrices, known as MClusters, with a fixed interconnection pattern to replace LUTs in field-programmable gate arrays (fpgas). To improve the efficiency of utilizing this structure, we design a SAT-based delay-aware packing algorithm to better utilize logical gates for the MCluster structure. Finally, we combine this algorithm with FPGA simulation tools to form a comprehensive benchmarking flow. A series of benchmark tests show that under the optimal design, up to 35% and 30% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS fpgas.

关键词： reconfigurable FET field-programmable gate arrays look-up table partitioning algorithm packing algorithm technology mapping performance benchmarking

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DOSA: Organic Compilation for Neural Network Inference on Distributed fpgas 7

DOSA: Organic Compilation for Neural Network Inference on Di...

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7th IEEE International conference on Edge computing and Communications (IEEE EDGE) / IEEE World Congress on Services (SERVICES)

作者： Ringlein, Burkhard Abel, Francois Diamantopoulos, Dionysios Weiss, Beat Hagleitner, Christoph Fey, Dietmar IBM Res Europe Ruschlikon Switzerland Friedrich Alexander Univ Erlangen Nurnberg Erlangen Germany

ISBN: (纸本)9798350304831

The computational requirements of artificial intelligence workloads are growing exponentially. In addition, more and more compute is moved towards the edge due to latency or localization constraints. At the same time, Dennard scaling has ended and Moore's law is winding down. These trends created an opportunity for specialized accelerators including field-programmable gate arrays (fpgas), but the poor support and usability of today's tools prevents fpgas from being deployed at scale for deep neural network (DNN) inference applications. In this work, we propose an organic compiler - DOSA - that drastically lowers the barrier for deploying fpgas. DOSA builds on the operation set architecture concept and integrates the DNN accelerator components generated by existing DNN-to-FPGA frameworks to produce an overall efficient solution. DOSA starts from DNNs represented in the community standard ONNX and automatically implements model- and data-parallelism, based on the performance targets and resource footprints provided by the user. Deploying a DNN using DOSA on 9 fpgas exhibits a speedup of up to 52 times compared to a CPU and 18 times compared to a GPU.

关键词： MLSys reconfigurable hardware Domain-specific architectures Compilers Distributed Artificial Intelligence Design Tools and Techniques

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A reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

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IEEE ACCESS 2023年 11卷 59438-59445页

作者： Kim, Victoria Heekyung Choi, Kyuwon Ken IIT Dept Elect & Comp Engn Chicago IL 60616 USA

In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile fpgas such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, an

关键词： INDEX TERMS FPGA accelerator CNN accelerator RT level design techniques low power techniques reconfigurable accelerator CNN-based object detection low power consumption high performance mobile FPGA

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FPGA Based Hardware Accelerator for Bio-Informatics applications 3

FPGA Based Hardware Accelerator for Bio-Informatics Applicat...

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3rd IEEE Asian conference on Innovation in technology, ASIANCON 2023

作者： Kate, Akash Khurge, Deepti Pimpri-Chinchwad College of Engineering Electronics and Telecommunication Engineering Pune India

ISBN: (纸本)9798350302288

We present the design and implementation of an FPGA-based accelerator for bioinformatics applications in this paper. To process large amounts of data generated by next generation sequencing (NGS) technologies, bioinformatics applications require high-performance computing capabilities. Because of their parallel processing capabilities and reconfigurable hardware, fpgas are a promising solution for accelerating bioinformatics applications. To achieve high throughput and low latency, the proposed accelerator architecture employs parallelism and pipelining. The FPGA accelerator's performance is compared to software implementations on a CPU. The results of the experiments show that the FPGA accelerator outperforms the CPU implementation. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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fpga-tidbits: Rapid Prototyping of FPGA Accelerators in Chisel 26

fpga-tidbits: Rapid Prototyping of FPGA Accelerators in Chis...

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26th Euromicro conference on Digital System Design (DSD) / 49th Euromicro conference on Software Engineering and Advanced applications (SEAA)

作者： Jellum, Erling Rennemo Umuruglu, Yaman Orlandic, Milica Schoeberl, Martin Norwegian Univ Sci & Technol Trondheim Norway Tech Univ Denmark Lyngby Denmark

ISBN: (纸本)9798350344196

With increasingly complex workloads and the end of Dennard scaling, the need for heterogeneous computing is becoming apparent. SoC fpgas (System-on-chip Field-Programmable Gate Arrays) are a promising solution to this need. They combine the versatility of CPUs and the reconfigurability and high performance of fpgas. SoC fpgas have received a great deal of attention in recent years from both academia and chipmakers. However, the task of hardware-software codesign, posed by these platforms, remains challenging. This is partly due to the lack of vendor-neutral abstractions for building and evaluating designs. Chisel is a promising hardware construction language based on the idea of writing hardware generators. In this paper, we present fpga-tidbits, an open-source, vendor-neutral Chisel library for rapid prototyping of accelerators for SoC fpgas.

关键词： Hardware-software codesign reconfigurable computing programmable logic

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