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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

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SoftCUDA: Running CUDA on Softcore GPU

SoftCUDA: Running CUDA on Softcore GPU

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Chihyo Ahn Ruobing Han Udit Subramanya Jisheng Zhao Blaise Tine Hyesoon Kim Georgia Institute of Technology USA University of California Los Angeles USA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Field-Programmable Gate Arrays (fpgas) have been extensively employed to accelerate parallel applications by allowing designers to customize their hardware for maximum performance. However, most FPGA-based designs are constrained to specific kernels, limiting their suitability across diverse workloads. As GPU workloads grow in complexity and their requirements diverge, softcore GPU(SoftGPU) designs have emerged to exploit FPGA reconfigurability for accelerating a broader range of parallel applications. Despite their potential, these designs have seen limited adoption due to the lack of comprehensive software stack support. In a CUDA-dominated development landscape, translating CUDA source code to alternative programming models can be challenging and often lacks direct feature parity. This paper introduces SoftCUDA, a novel framework that delivers comprehensive, end-to-end CUDA support on our SoftGPU, Vortex. By fully leveraging the reconfigurable architecture of SoftGPU and maintaining a user-friendly CUDA interface, SoftCUDA enables seamless integration and execution of unmodified CUDA applications on FPGA-based platforms.

关键词： Limiting Processor scheduling Source coding Instruction sets Graphics processing units Programming reconfigurable architectures Kernel Field programmable gate arrays Optimization

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A hardware acceleration Framework of reconfigurable Edge Modules for Convolutional Neural Networks

A hardware acceleration Framework of Reconfigurable Edge Mod...

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Annual conference of Industrial Electronics Society

作者： Yiming Qiao Zidi Jia Shixiang Li Lei Ren Beihang University Beijing China Zhongguancun Laboratory State Key Laboratory of Intelligent Manufacturing System Technology Beihang University Beijing China

ISBN: (数字)9781665464543

ISBN: (纸本)9781665464550

Edge computing exploits node devices situated in close proximity to terminals to deliver distributed computing services directly to users, with fpgas serving as the predominant platform. With the amplification in volume and intricacy of deep learning models, effectively deploying these models on FPGA devices introduces substantial challenges. To counter this predicament, this paper introduces an FPGA-based hardware acceleration framework for reconfigurable edge devices tailored for Convolutional Neural Networks (CNNs). Initially, a method for dynamically quantizing network models is devised to markedly curtail model memory consumption. Subsequently, a meticulously engineered hardware acceleration unit is formulated to attain augmented computing parallelism via meticulous temporal redesign. Finally, model deployment on FPGA devices for inference verification is showcased utilizing fully connected and convolutional neural networks as exemplars. On the MNIST dataset, the FPGA inference unit attains remarkable accuracy and computational efficiency in comparison to CPUs and GPUs

关键词： Industrial electronics Solid modeling Computational modeling Memory management Parallel processing Convolutional neural networks Distributed computing Field programmable gate arrays Hardware acceleration Edge computing

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A Performance Comparison of PathTracing on FPGA and GPU

A Performance Comparison of PathTracing on FPGA and GPU

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作者： Lilja, AntonVidefors, Markus KTH Royal Institute of Technology

Ray Tracing algorithms have long been the popular choice for rendering realistic images, and in recent years they have also reached the field of real time computer graphics. Although their performance has seen great improvement, they are still very computationally costly to perform, both in terms of time and power. Improving their performance and efficiency is therefore a very relevant field of research, to improve current applications and open up new possibilities for the future. In this degree project we have focused on implementing a ray tracing algorithm called Path Tracing on an Field Programmable Gate Array (FPGA), a type of reconfigurable hardware. fpgas provide a new path towards increasing performance as we approach the end of Moore's Law and reach the limits of general-purpose computing, making them an interesting candidate for ray tracing. This study resulted in a substantial performance difference between FPGA and GPU, with GPU outperforming FPGA by around 20 times in full path tracing.

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International conference on applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2022

International Conference on Applications in Electronics Perv...

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International conference on applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2022

ISBN: (纸本)9783031303326

The proceedings contain 52 papers. The special focus in this conference is on applications in Electronics Pervading Industry, Environment and Society. The topics include: Analysis, Design and Synthesis of an Execution Tracing Unit (ETU) Based on AUTOSAR Run-Time Interface (ARTI);a Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography;A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS technology;Affordance Segmentation Using RGB-D Sensors for Application in Portable Embedded Systems;ML-Based Classifier for Precision Agriculture on Embedded Systems;deep Reinforcement Learning for Automated Car Parking;Machine Learning Techniques for Anomaly-Based Detection System on CSE-CIC-IDS2018 Dataset;AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation;contextual Bandits Algorithms for reconfigurable Hardware Accelerators;efficient Uploading *** Datasets into a Non-Relational Database Management System;low-Cost Lithium-Ion Battery Characterization Setup Based on Auxiliary Batteries;model-Based Vital Control Architecture for Highly Automated Train Operations;exposure of the Human Head to 5G Electromagnetic Radiations: Modeling and Analysis;a Short-Range Free-Space Optical Communication System for Space-Assembled Microsatellites;A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS technology;sorting of Live/dead Escherichia Coli by Means of Dielectrophoresis for Rapid Antimicrobial Susceptibility Testing;soluble Mandrel technology to Produce Parts in Composite Material for Formula 1;A reconfigurable 2D-Convolution Accelerator for DNNs Quantized with Mixed-Precision;diagnostic Analytics for Pixelated Particle Detectors: A Case Study;developing a Toolchain for Synthetic Driving Scenario Datasets;microcontroller Based Edge computing for Pipe Leakage Detection;ticketing Systems for Smart Public Transportation: Tools at the User Side;Debris Detection

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Design, Implementation and Machine Learning Analysis of Frequency reconfigurable Microstrip Antenna for Defense applications

Design, Implementation and Machine Learning Analysis of Freq...

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2022 International conference on Sustainable computing and Data Communication Systems, ICSCDS 2022

作者： Durga, R.V. Haasya, G. Durga, D Shravani Nayak, S Narsimha Geethanjali College of Engineering and Technology Department of Electronics Comm. Engineering Hyderabad India

ISBN: (纸本)9781665478847

In this paper a Frequency reconfigurable antenna with a U-slot is designed with a high gain of 9.2dB and can be reconfigured from 1.61-1.68GHz, the analysis of reconfigurability aspect and the behaviour of lumped components is studied using Machine Learning. reconfigurable antennas are those which are capable of changing the resonant frequency based on the switching circuits used. These switching circuits use an additional load such as PIN Diodes, MEMS Switches etc., We considered PIN Diode since it is easy to design and is economical for our analysis in HFS S. The effect of each lumped component (R, L C) is individually studied and it is observed that R value has a correlation coefficient of 0.961 with return loss, and correlation coefficient of 0.090 is obtained for frequency. R value is said to have significant effect on reconfigurability aspect of the antenna. © 2022 IEEE.

关键词： Microstrip antennas

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Building Simulation Environment of reconfigurable Virtual Accelerator (ReVA) 30th

Building Simulation Environment of Reconfigurable Virtual A...

引用

30th International conference on Parallel and Distributed Processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied computing, CSCE 2024

作者： Kawai, Shunya Maeda, Eriko Yaguchi, Kazuki Osana, Yasunori Miyoshi, Takefumi Nakajo, Hironori Tokyo University of Agriculture and Technology Graduate School of Engineering Tokyo Japan Kumamoto University Research and Education Institute for Semiconductors and Informatics Kumamoto Japan WasaLabo LLC. Tokyo Japan Tokyo University of Agriculture and Technology Institute of Engineering Tokyo Japan

ISBN: (纸本)9783031856372

In recent years, research in AI and HPC has explored accelerating computations using fpgas. High-Level Synthesis (HLS) is beneficial for implementing algorithms from these fields onto fpgas as circuits. However, since the circuits generated by HLS are generally larger than those designed with HDL. Moreover, the operations in these fields tend to increase in number and complexity, and the FPGA resources required are increasing accordingly. Therefore, using fpgas in practice presents challenges regarding resource restrictions. To address these issues, we are researching reconfigurable Virtual Accelerator (ReVA), which allows the sharing of resources across multiple fpgas and enables the implementation of large-scale circuits. ReVA creates and shares virtual accelerators (VAs) using the resources of multiple fpgas. Processors and VAs in a ReVA share data using distributed shared memory (DSM). Furthermore, the data on the VA and DSM are dynamically arranged so that access from each of the processors used is the shortest. In this paper, we propose and implement ReVA Simulator. ReVA Simulator can reproduce ReVA operation without the need to prepare an actual device with an FPGA, processor and memory connected. Furthermore, we estimated the execution time when utilizing ReVA and conducted evaluations. The evaluation result shows that ReVA simulator achieves FFT reduced by 36% against execution in C. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： High level synthesis

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Implementation and Performance Evaluation of Memory System Using Addressable Cache for HPC applications on HBM2 Equipped fpgas 28th

Implementation and Performance Evaluation of Memory System...

引用

28th International European conference on Parallel and Distributed computing , Euro-Par 2022

作者： Fujita, Norihisa Kobayashi, Ryohei Yamaguchi, Yoshiki Boku, Taisuke Center for Computational Sciences University of Tsukuba Tsukuba Japan Degree Programs in Systems and Information Engineering Graduate School of Science and Technology University of Tsukuba Tsukuba Japan

ISBN: (纸本)9783031312083

When we apply field programmable gate arrays (fpgas) as HPC accelerators, their memory bandwidth presents a significant challenge because it is not comparable to those of other HPC accelerators. In this paper, we propose a memory system for HBM2-equipped fpgas and HPC applications that uses block RAMs as an addressable cache implemented between HBM2 and an application. This architecture enables data transfer between HBM2 and the cache bulk and allows an application to utilize fast random access on BRAMs. This study demonstrates the implementation and performance evaluation of our new memory system for HPC and HBM2 on an FPGA. Furthermore, we describe the API that can be used to control this system from the host. We implement RISC-V cores in an FPGA as controllers to realize fine-grain data transfer control and to prevent overheads derived from the PCI Express bus. The proposed system is implemented on eight memory channels and achieves 102.7 GB/s of the bandwidth. It overcomes the memory bandwidth of conventional FPGA boards with four channels of DDR4 memory despite using only 8 of 32 channels of the HBM2. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Data transfer

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reconfigurable computing Systems as Component-oriented Designs for Robotics 31

Reconfigurable Computing Systems as Component-oriented Desig...

引用

31st International conference on Field-Programmable Logic and applications (FPL)

作者： Podlubne, Ariel Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany Tech Univ Dresden Ctr Tactile Internet Human Loop CeTI Dresden Germany

ISBN: (纸本)9781665437592

Modern robotic platforms are increasingly complex due to incorporating various heterogeneous sensors and several actuators generating data at large frequencies. They are mostly based on embedded computers but relying on software solutions not entirely suited for parallel processing. fpgas are an ideal candidate to solve this issue, enhancing those systems' computing capabilities while still being programmable. We follow a holistic approach and study which components are needed for FPGA-based robotic applications. We propose a model-based component-oriented workflow to realize such applications. Its only input is a System's Specification to generate components to manage N accelerators, their behavior and interfaces to several middlewares. Only simple modifications to specifications rather than complex changes to implementations are needed to generate all these tailored components for any kind of robotic applications.

关键词： HWISW Co-Design Robotics Code Generation Model-Based Embedded Hardware fpgas

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PPM: A Privacy-Preserving Framework for Intelligent Medical Diagnosis Systems 17

PPM: A Privacy-Preserving Framework for Intelligent Medical ...

引用

17th IEEE International conference on Anti-Counterfeiting, Security, and Identification, ASID 2023

作者： Xia, Ruidan Huang, Chaolong Liu, Yining Peng, Ming Huang, Pingxiang Hefei University of Technology School of Microelectronics Hefei China

ISBN: (纸本)9798350319613

The extensive utilization of deep learning techniques has significantly boosted the efficacy of intelligent Computer-Aided Diagnosis (CAD) using medical data from multiple modalities. Deep learning techniques generally suffer from high computational complexity and cloud computing can effectively empower deep learning techniques by optimized software (e.g. distributed training/inference) and specific hardware (e.g. GPUs, fpgas and TPUs). However, cloud computing also increases the risk of medical data leakage, which greatly hurts patients' privacy. There has been several techniques including homomorphic encryption approach proposed to preserve patients' privacy. However, none of them can be directly applied to deep neural networks to improve medical CAD applications via multi-modal data fusion. In this paper, we propose PPM, a framework integrating semantic level multi-modal data fusion neural network with homomorphic encryption mechanism, in order to preserve patients' privacy while maintaining the diagnostic performance. We conduct experiments on multi-source and multi-modal medical data for Upper Gastrointestinal (UGI) cancer screening. © 2023 IEEE.

关键词： Learning systems

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Efficient Architecture for a High Performance Authenticated Encryption Algorithm on reconfigurable computing 9th

Efficient Architecture for a High Performance Authenticate...

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9th EAI International conference on Advancement of Science and technology, ICAST 2021

作者： Abebe, Abiy Tadesse Shiferaw, Yalemzewd Negash Kumar, P. G. V. Suresh School of Electrical and Computer Engineering Addis Ababa Institute of Technology AAU Addis Ababa Ethiopia Ambo University Ambo Ethiopia

ISBN: (纸本)9783030937089

High performance authenticated encryption algorithms are indispensable and preferable for securing the contemporary high speed wireless networks as they can perform their tasks without affecting overall performance of the network, and can provide data confidentiality, data integrity, and authentication cryptographic services simultaneously. Most of existing FPGA based architectures that have been proposed to enhance performance of such algorithms considered generic FPGA fabrics for implementations. Implementing complex algorithms using only traditional FPGA logic requires large amount of such resources that in turn can affect performance. In this work, an efficient architecture for AEGIS-128 authenticated encryption algorithm is proposed using both fpgas’ embedded hard-cores such as digital signal processing slices and block random access memories that have not been fully exploited for such applications with balanced amount of generic logic. The aim is to reduce performance bottlenecks and enhance performance of AEGIS-128. The implementation results show that the proposed architecture outperforms existing similar approaches found in the literature in terms of throughput, and utilization of reduced amount of resources. © 2022, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： Cryptography

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