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A real-time and high-performance MobileNet accelerator based on adaptive dataflow scheduling for image classification

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2024年第1期21卷 4-4页

作者： Sang, Xiaoting Ruan, Tao Li, Chunlei Li, Huanyu Yang, Ruimin Liu, Zhoufeng Zhongyuan Univ Technol Sch Elect & Informat Engn Zhengzhou 450007 Peoples R China China Patent Informat Ctr Beijing 100088 Peoples R China China Univ Petr East China Coll Oceanog & Space Informat Qingdao 266580 Peoples R China

Convolutional neural network (CNN) models equipped with depth separable convolution (DSC) promise a lower spatial complexity while retaining high model accuracy. However, little attention has been paid to their hardware architecture. Previous studies on DSC-based CNN accelerators typically use fixed computational models for various models, leading to an imbalance between power, efficiency, and performance. To address this problem, a novel, real-time DSC-based CNN accelerator that can accommodate field-programmable gate arrays (fpgas) of different capacities and CNNs of different sizes is proposed in this paper. Attractively, a dynamically reconfigurable computing engine and block-convolution-based adaptive dataflow scheduling mode strike a trade-off between hardware resources and the processing speed in industrial processes. The proposed MobileNet accelerator was implemented and evaluated on the Xilinx XC7020 platform. Compared to previous FPGA-based accelerators, the experimental results showed that our approach can provide 10.86 GOPS of computational performance for full HD RGB images, meeting the needs of real industrial real-time applications.

关键词： DSC-based CNN FPGA Real-time accelerator reconfigurable computing engine

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Joint Optimization of Maximum Achievable Rate in SWIPT Systems Assisted by Active STAR-RIS 18th

Joint Optimization of Maximum Achievable Rate in SWIPT Sys...

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18th International conference on Wireless Artificial Intelligent computing Systems and applications, WASA 2024

作者： Yang, Junlong Qin, Xizhong Jia, Zhenhong Mao, Lamu School of Computer Science and Technology XJU Xinjiang China Xinjiang Key Laboratory of Signal Detection and Processing Wulumuqi China

ISBN: (纸本)9783031714665

This investigation focuses on a simultaneous wireless information and power transfer (SWIPT) system, significantly enhanced by an active simultaneously transmitting and reflecting reconfigurable intelligent surface (aSTAR-RIS). It extends the degrees of freedom (DoF) for the system and addresses the "double fading" challenge seen in passive RIS frameworks. Our objective is the maximization of the sum achievable rate (SAR), achieved by optimizing the transmit beamforming vector at the base station (BS) and the coefficient and amplification matrices at the aSTAR-RIS. Through an alternating optimization (AO) strategy and fractional programming (FP), a sub-optimal solution is obtained. Simulations demonstrate that our aSTAR-RIS approach results in a 16.5% increase in performance over conventional active RIS configurations and a significant 114% improvement over passive STAR-RIS schemes. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Inductive power transmission

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A Survey on Hypervisor-based Virtualization of Embedded reconfigurable Systems 31

A Survey on Hypervisor-based Virtualization of Embedded Reco...

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31st International conference on Field-Programmable Logic and applications (FPL)

作者： Wulf, Cornelia Willig, Michael Goehringer, Diana Tech Univ Dresden Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781665437592

The increase of size, capabilities, and speed of fpgas enables the shared usage of reconfigurable resources by multiple applications and even operating systems. While research on FPGA virtualization in HPC-datacenters and cloud is already well advanced, it is a rather new concept for embedded systems. The necessity for FPGA virtualization of embedded systems results from the trend to integrate multiple environments into the same hardware platform. As multiple guest operating systems with different requirements, e.g., regarding real-time, security, safety, or reliability share the same resources, the focus of research lies on isolation under the constraint of having minimal impact on the overall system. Drivers for this development are, e.g., computation intensive AI -based applications in the automotive or medical field, embedded 5G edge computing systems, or the consolidation of electronic control units (ECUs) on a centralized MPSoC with the goal to increase reliability by reducing complexity. This survey outlines key concepts of hypervisor-based virtualization of embedded reconfigurable systems. Hypervisor approaches are compared and classified into FPGA-based hypervisors, MPSoC-based hypervisors and hypervisors for distributed embedded reconfigurable systems. Strong points and limitations are pointed out and future trends for virtualization of embedded reconfigurable systems are identified.

关键词： Hypervisor FPGA Virtualization Virtual Machine Embedded Real-Time

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RECO-HCON: A High-Throughput reconfigurable Compact ASCON Processor for Trusted IoT 35

RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Pr...

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35th IEEE International System-on-Chip conference (SOCC)

作者： Wei, Xiangdong El-Hadedy, Mohamed Mosanu, Sergiu Zhu, Zhengping Hwu, Wen-Mei Guo, Xinfei Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai Peoples R China Calif State Polytech Univ Pomona Dept Elect & Comp Engn Pomona CA USA Univ Illinois Coordinated Sci Lab Urbana IL USA Univ Virginia Charlottesville VA USA

ISBN: (数字)9781665459853

ISBN: (纸本)9781665459853

Statistics show that in 2030 the number of connected IoT devices will reach 25.44 billion, which can lead to the security breach in the back-end of high-performance computing clusters connected with the same network. Unfortunately, the current security primitives are not suitable algorithms to be implemented on physically constrained devices designed for IoT. Thus, the National Institute of Standard and technology has announced a worldwide lightweight cryptographic competition (LWC) for securing tiny devices. This paper introduces a flexible, reconfigurable, and energy-efficient crypto-processor running one of the LWC finalist candidates - ASCON, which uses sponge construction that has fewer memory accesses that leads to less power consumption compared to other ones. The proposed processor is reconfigurable in a way both authenticated cipher (Encryption/decryption processes) and hash functions of ASCON are implemented in a six-mode compact fashion, covering a diversity of applications in the IoT spectrum. The design is developed in Chisel and evaluated in 28/32nm technology with commercial EDA tools. Evaluation results show that the proposed processor achieves the highest throughput while consuming 29% less power, operating at over 667 MHz. The design has also been implemented in Skywater 130nm technology node with the latest released OpenLane design flow to ensure an end-to-end open-source delivery of the IP.

关键词： LWC ASCON FPGA reconfigurable computing ASIC

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An Optimized Topology for High-Performance reconfigurable computing. Part I: Analysis of 2D and 3D NoC Topologies

An Optimized Topology for High-Performance Reconfigurable Co...

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Emerging Trends in Engineering, Sciences and technology (ICES&T), IEEE International conference on

作者： Qaiser Ijaz El-Bay Bourennane ImViA Laboratory University of Burgundy Dijon France

With a pledge to improve the performance per watt, fpgas have earned a place in the world’s leading center for high-performance computing, which has opened new avenues for research. In pursuit of an optimized topology in the context of reconfigurable computing, we analyzed six selected 2D and 3D NoC topologies. The results showed that the 3D Torus demonstrated significant throughput as network size, the number of nodes transferring messages, and message size varied. Based on performance analysis and anticipated acceptable resource utilization, we singled out the 3D Torus for further investigation and optimization.

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The FPGA Implementation of Pseudorandom Word Generation Algorithms 12

The FPGA Implementation of Pseudorandom Word Generation Algo...

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12th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems: technology and applications, IDAACS 2023

作者： Opanasenko, Volodymyr Zavyalov, Stanislav V.M. Glushkov Institute of Cybernetics of Nas of Ukraine Department of Microprocessor Devices Kyiv03187 Ukraine Radionix Limited Company Kyiv03187 Ukraine

ISBN: (纸本)9798350358056

This paper introduces a novel FPGA-based hardware implementation of a pseudorandom word (PSW) generator. Using the FPGA reconfiguration property, the proposed approach allows you to change the algorithms and replace the online structure during the generator. The integration of embedded digital signal processing (DSP) blocks within the FPGA chip allows for the efficient implementation of the pseudorandom bit generator by leveraging fundamental operations like multiplication with accumulation at the gate level. The PSW generator's design and implementation are performed using the VHDL language and the CAD tool ISE 14.02 Foundation. The implementation is carried out on a Spartan-based series chip (6SLX4CSG225-3), and the paper provides a comprehensive analysis of the time and hardware costs associated with three different types of pseudorandom word generators. To validate the effectiveness of the designs, the simulation results are obtained using the ModelSim SE 10.1c, and timing diagrams are presented for these structures. © 2023 IEEE.

关键词： bit sequence generation CAD DSP FPGA generator of pseudo-random sequences random number generation reconfigurable logic simulation modeling statistical randomness

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HBM2 Memory System for HPC applications on an FPGA

HBM2 Memory System for HPC Applications on an FPGA

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IEEE International conference on Cluster computing (Cluster)

作者： Fujita, Norihisa Kobayashi, Ryohei Yamaguchi, Yoshiki Boku, Taisuke Univ Tsukuba Ctr Computat Sci Tsukuba Ibaraki Japan Univ Tsukuba Fac Engn Informat & Syst Tsukuba Ibaraki Japan

ISBN: (纸本)9781728196664

Field Programmable Gate Arrays (fpgas) have been targeted as a new accelerator of the HPC field. This is because the barrier to using fpgas has been gradually lowered due to the widespread use of high-level synthesis (HLS) technology. In addition, the bandwidth of external memory in fpgas is much lower than that of other accelerators widely used in HPC, such as NVIDIA V100 GPUs. However, the latest fpgas can use High Bandwidth Memory 2 (HBM2), which has a memory bandwidth of up to 512GB/s. Therefore, we believe fpgas will be a viable option for speeding up applications. However, unlike CPUs and GPUs, fpgas do not have caches and memory networks to exploit the full potential of HBM2, which may limit the efficiency of the application. In this paper, we propose a memory system for HBM2 and HPC applications. We show the prototype implementation of the system and evaluate its performance. We also demonstrate the use of the proposed system from an application developed in High -Level Synthesis (HLS) written in C++.

关键词： FPGA High Bandwidth Memory 2 Memory Network High-Level Synthesis

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Monolithic Frequency-reconfigurable Antenna on Silicon Carbide for Constrained Environments

Monolithic Frequency-Reconfigurable Antenna on Silicon Carbi...

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2023 IEEE conference on Antenna Measurements and applications, CAMA 2023

作者： Allanic, Rozenn Le Berre, Denis Quendo, Cedric Ball, Edward A Shien Ng, Jo Huang, Guanwei Leuliet, Aude Merlet, Thomas Univ. Brest Lab-STICC CNRS UMR 6285 Brest France The University of Sheffield Dept of Electronic & Electrical Engineering Sheffield United Kingdom Thales Las Ome Élancourt France

ISBN: (纸本)9798350323047

The paper presents a frequency reconfigurable bowtie antenna designed on silicon carbide (SiC) substrate. A monolithic active antenna is achieved thanks to the co-design method between the active integrated junctions and the bowtie antenna. Indeed, the semiconductor substrate allows doping distributed areas to obtain integrated N+P+ junction into the substrate co-designed in a same process flow as the antenna. When the junctions are forward biased, they connect a pair of stubs to the antenna creating a second resonant frequency. The global co-design approach offers possibilities to optimize the antenna in both frequencies. In the prototype, the resonant frequency can be switched from 20.5 GHz to 17.3 GHz. © 2023 IEEE.

关键词： Silicon carbide

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Efficient Hardware Acceleration of Spiking Neural Networks Using FPGA: Towards Real-Time Edge Neuromorphic computing

Efficient Hardware Acceleration of Spiking Neural Networks U...

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IEEE conference on Vehicular technology (VTC)

作者： Soukaina El Maachi Abdellah Chehri Rachid Saadane Intelligent Systems and Sensor Networks (SIRC) Hassania School of Public Works - (EHTP) Casablanca Morocco Department of Mathematics and Computer Science Royal Military College of Canada Kingston Canada

ISBN: (数字)9798350387414

ISBN: (纸本)9798350387421

This paper examines the critical function of Field-Programmable Gate Arrays (fpgas) in speeding Spiking Neural Networks (SNNs) for real-time edge neuromorphic computing. Our work systematically evaluates the integration of FPGA technology for the optimization and speeding of SNN models. The analysis covers the power efficiency, low latency processing, and parallelism that are intrinsic benefits of fpgas, emphasizing their relevance for edge computing applications. We discuss the smooth transfer of trained SNN models to FPGA platforms. Using an extensive analysis of state-of-the-art architectures, we demonstrate the efficiency benefits of using FPGA to accelerate SNNs. We derive more insights into the real-world applications of this FPGA-SNN integration in various fields. The analysis supports advances in edge computing and neuromorphic processing paradigms by adding to the collective knowledge of how FPGA enhances the real-time processing capabilities of Spiking Neural Networks.

关键词： Vehicular and wireless technologies Neuromorphic engineering Computational modeling Spiking neural networks Real-time systems Field programmable gate arrays Optimization

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Heterogeneous reconfigurable Accelerators: Trends and Perspectives 23

Heterogeneous Reconfigurable Accelerators: Trends and Perspe...

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Proceedings of the 60th Annual ACM/IEEE Design Automation conference

作者： Wayne Luk Department of Computing Imperial College London UK

ISBN: (纸本)9798350323481

Heterogeneity and reconfigurability have both been adopted by accelerators to improve their flexibility and efficiency for a wide variety of applications, from cloud computing to embedded systems. This paper provides an overview of the trends of heterogeneous reconfigurable accelerators including field-programmable gate arrays and coarse-grained reconfigurable arrays, and the related design automation approaches for enhancing design quality and designer productivity of these accelerators. We shall also discuss how recent advances in technology, such as multi-level co-design, heterogeneous Function-as-a-Service and meta-programming, would help address the challenges in engineering next-generation heterogeneous reconfigurable accelerators and beyond.

关键词： accelerator

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