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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是241-250 订阅

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Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile fpgas

Towards High-Throughput Neural Network Inference with Comput...

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Design, Automation and Test in Europe conference and Exhibition

作者： Hao Zhang Mengying Zhao Huichuan Zheng Yuqing Xiong Yuhao Zhang Zhaoyan Shen School of Computer Science and Technology Shandong University China Department of Computer Science and Technology Tsinghua University China

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

Field-programmable gate arrays (fpgas) have been widely used in artificial intelligence applications. As the capacity requirements of both computation and memory resources continuously increase, emerging nonvolatile memory has been proposed to replace static random access memory (SRAM) in fpgas to build nonvolatile fpgas (NV-fpgas), which have advantages of high density and near-zero leakage power. Features of emerging nonvolatile memory should be fully explored to improve performance, energy efficiency as well as lifetime of NV-fpgas. In this paper, we study an intrinsic characteristic of emerging nonvolatile memory, i.e., computing-in-memory, in nonvolatile block random access memory (BRAM) of NV-fpgas. Specifically, we present a computational BRAM architecture (C-BRAM), and propose a computational density aware operator allocation strategy to fully utilize C-BRAM. Neural network inference is taken as an example to evaluate the proposed architecture and strategy, showing 68% and 62% improvement in computational density compared to traditional SRAM-based FPGA and existing NV-FPGA, respectively.

关键词： Nonvolatile memory Neural networks Memory management Random access memory Energy efficiency Resource management Artificial intelligence

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Efficient Regular Expression Matching and Hardware-Accelerated Finite Automata Pattern Recognition in NIDS 6

Efficient Regular Expression Matching and Hardware-Accelerat...

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6th International conference on Recent Trends in Advance computing, ICRTAC 2023

作者： Thota, Krishna Kishore Retna Raj, R. Jeberson Sathyabama Institute of Science and Technology Department of Computer Science and Engineering Tamilnadu India

ISBN: (纸本)9798350394702

To protect network infrastructure from the ever-changing cyber threats, Intrusion Detection Systems (IDS) perform important duties. This study introduces a sophisticated algorithm aimed at overcoming key challenges in IDS. These challenges include efficient regular expression matching, hardware implementation, and improved pattern recognition. The algorithm employs a unique technique to reduce memory specifications by using controlled faults into the pattern matching process. It builds upon perfect hashing, ensuring precise and efficient regular expression matching, making it ideal for high-speed processing in IDS applications. Additionally, the central component of a hardware-based Network Intrusion Detection System (NIDS), the technique comprises a signature match processor that is based on a field-programmable gate array (FPGA). For effective string matching, this processor makes use of a CAM-based cellular architecture. For multiple signature matches, it generates priority-encoded addresses using a binary tree structure. To enhance IDS capabilities further, the algorithm introduces an efficient method for detecting regular expression matches within network traffic text using Field-Programmable Gate Arrays (fpgas). It presents a hardware implementation approach based on Deterministic Finite Automata (DFA), enhancing both speed and accuracy in pattern matching. This proposed algorithm provides a comprehensive solution to optimize intrusion detection by integrating innovative techniques in regular expression matching, hardware acceleration, and pattern recognition, thereby enhancing network security against springing cyber threats. © 2023 IEEE.

关键词： Cryptography

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GIM: Versatile GNN Acceleration with reconfigurable Processing-in-Memory 41

GIM: Versatile GNN Acceleration with Reconfigurable Processi...

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41st IEEE International conference on Computer Design (ICCD)

作者： Nie, Chen Chen, Guoyang Zhang, Weifeng He, Zhezhi Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai Peoples R China Alibaba Cloud Infrastruct Sunnyvale CA USA

ISBN: (纸本)9798350342918

Recent boost of deep learning has revolutionized many machine learning tasks, including the graph neural networks (GNNs) that are specifically designed for non-Euclidean graph data. GNNs have been widely adopted in numerous real-world applications, such as the recommendation system. However, with increasingly enlarged graph size and complexity, GNN performance on conventional computers has been severely hindered by the memory bottleneck. The challenge attracts wide investigations, and the processing-in-memory (PIM) architecture arises as one of the most promising solutions. Prior works have leveraged the ReRAM crossbars as analog dot-product engines to accelerate the vector-matrix multiplications in GNN, and achieve prominent performance improvements over modern CPUs and GPUs. Nevertheless, analog computing is known to be variation-vulnerable, which hampers the inference accuracy of GNN. Besides, the mixed-signal peripherals (e.g., ADC) are hardware-expensive and specialize in dense computations, which makes the analog crossbar-based PIM not the ideal candidate for GNN inference whose computation is of great sparsity. In this work, we propose a novel digital-PIM architecture for GNN acceleration, namely GIM. Our compact yet efficient digital computing paradigm can greatly boost computing parallelism with a minimum budget. GIM integrates dedicated optimizations on both operand- and bit-sparsity, to eliminate sparse computations thus significantly boost the performance. Meanwhile, at the software level, we implement data-layout optimizations to minimize the inter-memory communications and maximize computing parallelism. Our design derives prominent performance improvements over the modern CPU, GPU, and state-of-the-art PIM-based accelerators. Compared to modern CPU and GPU, GIM averagely achieves 24485x and 778x of speedup, and 78480x and 8906x of energy reduction. Compared to the state-of-the-art PIM-based GNN accelerators ReFlip and PIMGCN, GIM averagely achieves 9.

关键词： graph neural network processing-in-memory

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COPRAO: A Capability Aware Query Optimizer for reconfigurable Near Data Processors 37

COPRAO: A Capability Aware Query Optimizer for Reconfigurabl...

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37th IEEE International conference on Data Engineering (IEEE ICDE)

作者： Lekshmi, B. G. Meyer-Wegener, Klaus Friedrich Alexander Univ Data Management CS6 Erlangen Germany

ISBN: (纸本)9781665448901

Placing the processing power near the data, rather than shipping the data to the processor is inevitable and demanding in the era of Big Data. Thereby near-data processors gained much attention in recent years as they can reduce the massive data transfer between data sources and computing nodes. However, it is important to rethink the computing architecture to achieve the maximum advantage of near-data-processing technology, particularly for query-processing applications. In this paper, we propose a new approach to the query optimization in a relational DBMS, which considers the specialized computing capabilities of the attached FPGA-based near-data processors. The paper focuses on the hardware-conscious optimization using extended rules and cost models as well as on refining the optimization strategies for changes in the hardware state of execution. Our evaluations demonstrate that the proposed query-optimization approach can improve the processing of queries using near-data processors based on fpgas.

关键词： Query optimization FPGA Near-data processor Hardware capability

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LAWS: Large-Scale Accelerated Wave Simulations on fpgas 23

LAWS: Large-Scale Accelerated Wave Simulations on FPGAs

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Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

作者： Dimitrios Gourounas Bagus Hanindhito Arash Fathi Dimitar Trenev Lizy John Andreas Gerstlauer The University of Texas at Austin Austin TX USA ExxonMobil Technology and Engineering Irving TX USA

ISBN: (纸本)9781450394178

computing numerical solution to large-scale scientific computing problems described by partial differential equations is a common task in high-performance computing. Improving their performance and efficiency is critical to exa-scale computing. Application-specific hardware design is a well-known solution, but the wide range of kernels makes it infeasible to provision supercomputers with accelerators for all applications. This makes reconfigurable platforms a promising direction. In this work, we focus on wave simulations using discontinuous Galerkin solvers, as an important class of applications. Existing work using fpgas is limited to accelerating specific kernels or small problems that fit into FPGA BRAM. We present LAWS, a generic and configurable architecture for large-scale accelerated wave simulation problems running on fpgas out of DRAM. LAWS exploits fine- and coarse-grain parallelism using a scalable array of application-specific cores, and incorporates novel dataflow optimizations, including prefetching, kernel fusion, and memory layout optimizations to minimize data transfers and maximize DRAM bandwidth utilization. We further accompany LAWS with an analytical performance model that allows for scaling across technology trends and architecture configurations. We demonstrate LAWS on the simulation of elastic wave equations. Results show that a single FPGA core achieves 69% higher performance than 24 Xeon cores with 13.27x better energy efficiency, when given 1.94x less peak DRAM bandwidth. Scaling to the same peak DRAM bandwidth shows that an FPGA is 3.27x and 1.5x faster than 24 CPU cores and an Nvidia P100 GPU, with 22.3x and 4.53x better efficiency, respectively.

关键词： wave simulations fpgas HPC discontinuous Galerkin

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Performance Estimation and Prototyping of reconfigurable Near-Memory computing Systems

Performance Estimation and Prototyping of Reconfigurable Nea...

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International conference on Field Programmable Logic and applications

作者： Veronia Iskandar Mohamed A. Abd El Ghany Diana Goehringer Chair of Adaptive Dynamic Systems Technische Universität Dresden Germany Electronics Department IES Lab German University in Cairo Egypt TU Darmstadt Germany Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI) Dresden/Leipzig Germany

The concept of near-memory computing (NMC) has emerged as a promising solution to address the memory wall challenges faced by future computing architectures. By utilizing modern systems that integrate 3D-stacked DRAM memory, the NMC paradigm minimizes unnecessary data movement between the memory subsystem and the CPU. FPGA vendors have incorporated 3D-stacked memories into their products to meet the increasing bandwidth requirements of memory-intensive applications, enabling fpgas to compete with GPU solutions in terms of speed and energy efficiency. Recent NMC proposals focus on different data processing workloads, including graph processing and machine learning. This work addresses the research questions of how to leverage the full bandwidth of 3D-stacked high-bandwidth memory and how to facilitate the adoption of the near-memory computing paradigm.

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A Dynamic Logic Based reconfigurable Digital CIM Macro for Edge computing

A Dynamic Logic Based Reconfigurable Digital CIM Macro for E...

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IEEE International conference on Circuits and Systems (ICCS)

作者： Yingbo Hao Huangxu Chen Yi Zou Yanfeng Yang School of Microelectronics South China University of Technology Guangzhou China

ISBN: (数字)9798350352153

ISBN: (纸本)9798350352160

The imperative for energy efficiency in Artificial Intelligence (AI) aligns with global environmental sustainability goals, presenting substantial challenges. Compute-in-memory (CIM) offers a viable solution for edge computing, capitalizing on its superior energy efficiency and bandwidth. Yet, the specialized nature of CIM hardware impedes its broader adoption in AIoT applications. This study introduces a dynamically reconfigurable digital CIM leveraging dynamic logic to enhance energy efficiency. Dynamic logic reduces transistor count and transmission delay compared to static logic, thereby augmenting the energy efficiency ratio. It features a reconfigurable Manchester carry chain for adaptable computation across different data bit-widths and incorporates reusable computation units supporting seven operator types, minimizing circuit area. Evaluation using TSMC 40-nm CMOS technology demonstrates that the proposed macro circuit operates at 800 MHz at 1.1 V, achieving energy efficiencies of 0.76 TOPS/W for 8-bit multiplication and 4.22 TOPS/W for 8-bit addition at 0.8 V. Emulation of neural networks (NNs) within the AIoT framework demonstrates that a significant number of computational cycles can be executed using a minimal set of instructions.

关键词： Emulation Artificial neural networks In-memory computing Energy efficiency Common Information Model (computing) Logic Internet of Things Transistors Artificial intelligence Edge computing

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FPGA-Based Accident Prevention System for Autonomous Vehicles

FPGA-Based Accident Prevention System for Autonomous Vehicle...

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2022 IEEE International conference on Advances in computing, Communication and Applied Informatics, ACCAI 2022

作者： Perumal, Vivek Karthick Siralan, R. Sivadharseni, S. Sona College of Technology. Salem Department of ECE Tamil Nadu India

ISBN: (纸本)9781665495295

Traveling is a basic necessity for human life style has now turned to be dangerous. Accidents are proportionally increasing with time. WHO reports an average of 1.3 million people die per year as a result of road traffic crashes. This white paper speaks about a system that employs Field Programmable Gate Arrays (fpgas) based hardware implementation for objects representation incorporates ultrasonic sensors and cameras, along with virtual confirmation. Furthermore, the alert system can automatically be turned on and shows the exact status of the vehicles around. The proposed system uses a field-programmable gate array (FPGA), promising a cheaper design with the implementation of various applications that needs real-Time, fast, and reliable data processing which is more efficient and flexible. Hence, our system can be used for Real-Time tracking and Accident prevention. © 2022 IEEE.

关键词： Cameras

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14th IFIP WG 5.5/SOCOLNET Advanced Doctoral conference on computing, Electrical and Industrial Systems, DoCEIS 2023

14th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Co...

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14th IFIP WG 5.5/SOCOLNET Advanced Doctoral conference on computing, Electrical and Industrial Systems, DoCEIS 2023

ISBN: (纸本)9783031360060

The proceedings contain 22 papers. The special focus in this conference is on computing, Electrical and Industrial Systems. The topics include: Cleaning ECG with Deep Learning: A Denoiser Based on Gated Recurrent Units;exploring Kolmogorov Complexity Approximations for Data Analysis: Insights and applications;clinical Data Integration Strategies for Multicenter Studies;support Operation and Maintenance of Power Wheelchairs with Digital Twins: The IoT and Cloud-Based Data Exchange;preliminary Verification of Liveness in a Control Part of Cyber-Physical Systems Modeled by a Petri Net;QiBERT - Classifying Online Conversations: Messages with BERT as a Feature;supply Chain Quality Improvement Based on Customer Compliance;monte Carlo Simulation Applicable for Predictive Algorithm Analysis in Aerospace;a Load Balancing Mechanism for 3D Network-on-Chip with Partially Vertically Connected Links;a Collaborative Dimension for Renewable Energy Communities;enhancing Dynamism of IoT Service Composition;Systematic Design Methodology for Optimization of Voltage Comparators in CMOS technology;trans-Boolean Cyber Physical Systems;storage System for Energy Communities;renewable Energy Communities in Africa: A Case Study of Five Selected Countries;optimal Load Shedding for Smart Power Grid Resilience Enhancement Considering Cyber-Physical Constraints;superconducting Saturable Core Reactor as Variable Inductance for Controlling the Power Flow in a Transmission Line;an Overview of the Functions of Smart Grids Associated with Virtual Power Plants Including Cybersecurity Measures;a Bio-inspired and Altruistic-Based Framework to Support Collaborative Healing in a Smart Manufacturing Shop-Floor;reconfigurable Framework for Data Extraction Using Interoperable Brokers in Manufacturing.

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Nanotechnology-Enhanced Multipliers: Leveraging FinFET and GnrFET in Advanced Digital Systems 2

Nanotechnology-Enhanced Multipliers: Leveraging FinFET and G...

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2nd IEEE International conference on Integrated Intelligence and Communication Systems, ICIICS 2024

作者： Kumar, Pala Mahesh Rose Victor, J. Shron Purna Chandra Reddy, V. Udaya Sree, G. Sirisha, R. Krishna, Namani Vamshi SAK Informatics Hyderabad India Department of ECE Pragathi Engineering College Surampalem India Department of ECE G Narayanamma Institute of Science and Technology Hyderabad India Department of ECE St. Martin’s Engineering College Secunderabad India Department of MBA SRKR Engineering College Bhimavaram India

ISBN: (纸本)9798331504960

Multipliers find applications in high-performance computing and advanced digital systems, where speed and energy efficiency are crucial. Existing Fin Field Effect Transistor (FET) multipliers face challenges such as high-power consumption and significant propagation delays due to limitations in scaling and increased short-channel effects. These issues hinder performance and efficiency significantly as technology nodes shrink. The proposed Dynamic Path Auto-Configurable Multipliers (DPAM) leverages FET (FinFET) and graphene nanoribbon FET (GnrFET) technologies to enhance speed and reduce power consumption. By incorporating reconfigurable Booth Encoding (RBE), the multiplier efficiently handles large data values with reduced complexity and increased speed. The Dynamic Path Auto-configuration Adder (DPAA) optimizes the carry propagation paths, improving performance and energy efficiency. Integrating these advanced technologies results in a multiplier with superior characteristics compared to conventional designs. The performance metrics of DPAM include Total Path Delay (TPD) at 44.681 ns, Carry Out Rise Delay (CORD) at 43.180 ps, and Carry Out Fall Delay (COFD) at 40.902 ps, indicating efficient signal propagation. The Sum Rise Delay (SRD) is recorded at 43.190 ns, and the Sum Fall Delay (SFD) is 44.756 ns, showcasing balanced and stable operational delays. These values reflect the system's optimized delay characteristics for high-speed computational tasks. © 2024 IEEE.

关键词： FinFET

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