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IEEE 2nd German Education conference (GECon)

作者： Al Amin, Rashed Wiese, Veit Rahman, Mohammad Musfiqur Jacobs, Sven Jaschke, Steffen Obermaisser, Roman Univ Siegen Inst Embedded Syst Siegen Germany Univ Siegen Comp Sci Educ Siegen Germany

ISBN: (纸本)9798350348132

reconfigurable System-on-Chip (SoC) is a computing architecture that allows users to program and reprogram the hardware to perform different tasks, making it highly flexible and adaptable. Due to its potential to significantly accelerate various applications, reconfigurable SoC has become a subject of much research for academicians and industry. On the other hand, the classical practice of experimenting in the laboratory has been changing radically with the advanced utilization of computers, electronic devices, and the internet. As a result, it has given birth to a new concept of laboratory practice called Internet-of-Things (IoT) based collaborative simulation laboratory, which enables students to access and use the laboratory equipment at their convenience, enabling them to learn at their own pace and comfort. First, this paper reviewed the state of the art of reconfigurable SoC, specially Field-Programmable Gate Arrays (fpgas) laboratory architecture. Then, it developed an IoT-based collaborative simulation laboratory for reconfigurable SoC, allowing multiple students to work together to solve laboratory tasks remotely. Furthermore, this laboratory architecture is for reconfigurable fpgas, which can manage several tasks automatically, such as logic synthesis, logic simulation, and FPGA run from multiple fpgas or SoC. In addition to its benefits, the capability to virtualize user input/output interfaces and remotely measure the design's response further enhances its advantages. However, this proposed laboratory architecture is essential not only for doing laboratory tasks remotely but also simplifies the existing teaching methods and helping evaluate student performance in the examination.

关键词： system-on-chip field-programmable gate array internet-of-things remote laboratory

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BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native applications

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2022年第2期15卷 1–27页

作者： Damiani, Andrea Fiscaletti, Giorgia Bacis, Marco Brondolin, Rolando Santambrogio, Marco D. Politecn Milan DEIB Via Ponzio 34-5 I-20133 Milan Italy

"Cloud-native" is the umbrella adjective describing the standard approach for developing applications that exploit cloud infrastructures' scalability and elasticity at their best. As the application complexity and user-bases grow, designing for performance becomes a first-class engineering concern. As an answer to these needs, heterogeneous computing platforms gained widespread attention as powerful tools to continue meeting SLAB for compute-intensive cloud-native workloads. We propose BlastFunction, an FPGA-as-a-Service full-stack framework to ease fpgas' adoption for cloud-native workloads, integrating with the vast spectrum of fundamental cloud models. At the IaaS level, BlastFunction time-shares FPGA-based accelerators to provide multitenant access to accelerated resources without any code rewriting. At the PaaS level, BlastFunction accelerates functionalities leveraging the serverless model and scales functions proactively, depending on the workload's performance. Further lowering the fpgas' adoption barrier, an accelerators' registry hosts accelerated functions ready to be used within cloud-native applications, bringing the simplicity of a SaaS-like approach to the developers. After an extensive experimental campaign against state-of-the-art cloud scenarios, we show how BlastFunction leads to higher performance metrics (utilization and throughput) against native execution, with minimal latency and overhead differences. Moreover, the scaling scheme we propose outperforms the main serverless autoscaling algorithms in workload performance and scaling operation amount.

关键词： Field Programmable Gate Arrays (fpgas) cloud-native time-sharing autoscaling hardware acceleration

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Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based reconfigurable Processor (MRP)

Deep-BMNN: Implementing Sparse Binary Neural Networks in Mem...

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International Technical conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)

作者： Sasagawa, Kenta Wang, Senling Nishikawa, Tetsuya Kai, Hiroshi Higami, Yoshinobu Takahashi, Hiroshi Yotsuyanagi, Hiroyuki Ni, Tianming Wen, Xiaoqing Ehime Univ Matsuyama Ehime Japan Tokushima Univ Tokushima Japan Anhui Polytech Univ Wuhu Peoples R China Kyushu Inst Technol Kitakyushu Fukuoka Japan

ISBN: (纸本)9798350379068;9798350379051

The Memory-based reconfigurable Processor (MRP) is a memory-centric reconfigurable device that offers advantages in processing speed and cost compared to other reconfigurable devices like fpgas, making it a promising alternative device for Artificial Intelligence applications such as neural networks (NNs). However, due to the unique structure of MRP, the method for implementing NNs on it has not yet been established. In our previous work [8], we have proposed a sparse neural network model named MNN (MRP Neural Networks), specifically designed to align with the unique connection structure of MRP for neural network integration. This paper extends our research by proposing a binarization method for MNN referred to as the BMNN using XNOR-Net to facilitate practical NNs application (handwriting digits recognition) on MRP. To enhance the performance of BMNN, a novel implementation strategy Deep-BMNN is also proposed aimed at increasing both the layer depth and the neuron count of BMNN by folding the logic routing on the MRP device. Experimental results using MNIST dataset for handwritten digits recognition demonstrate that our proposed binary NNs for MRP can achieve comparable accuracy to those of fully connected NNs employing real numbers.

关键词： reconfigurable device MRP Neural Networks Binarization LUT In-Memory computing

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FPGA-ACCELERATED SIMULATION technology RESEARCH TO UNLOCKING POWERFUL COMPUTATIONAL CAPABILITIES

FPGA-ACCELERATED SIMULATION TECHNOLOGY RESEARCH TO UNLOCKING...

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2024 International conference on Electrical Engineering and Intelligent Control, EEIC 2024

作者： Ji, Wenyu Department of Electrical and Electronic Engineering University of Nottingham Ningbo China Ningbo315154 China

ISBN: (纸本)9781837242672

Conventional software-based simulation methodologies sometimes face challenges in keeping pace with the increasing intricacy and scale of contemporary computing problems. This article examines the ability of FPGA-accelerated simulation technologies to meet the increasing requirements of contemporary computing. Field-programmable gate arrays (fpgas) provide parallel processing capabilities and a reconfigurable architecture, providing a notable edge over conventional software-based simulation techniques. This results in enhanced speed, accuracy, and flexibility. The research examines the historical progression and present developments in FPGA technology, emphasizing its utilization in diverse fields such as multiphysics simulations, power systems, and machine control systems. The efficacy of FPGA acceleration in improving simulation performance is showcased using case studies and practical examples. Although there are difficulties associated with the intricate nature of FPGA design and its integration with current systems, the outlook for FPGA-accelerated simulations is optimistic. This is due to developments in AI-specific cores, heterogeneous computing, and the availability of cloud-based FPGA services, which are expected to facilitate wider acceptance and usage. This study asserts that FPGA-accelerated simulation technology is currently leading the way in computational innovation. It offers crucial tools to address the intricacy and magnitude of modern computational difficulties. © The Institution of Engineering & technology 2024.

关键词： reconfigurable architectures

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Constraint-Aware Multi-Technique Approximate High-Level Synthesis for fpgas

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2023年第4期16卷 1-28页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Inst Informat Fed Univ Rio Grande Do Sul 9500 Bento Gonc Alves Ave BR-91501970 Porto Alegre RS Brazil

Numerous approximate computing (AC) techniques have been developed to reduce the design costs in error-resilient application domains, such as signal and multimedia processing, data mining, machine learning, and computer vision, to trade-off computation accuracy with area and power savings or performance improvements. Selecting adequate techniques for each application and optimization target is complex but crucial for high-quality results. In this context, Approximate High-Level Synthesis (AHLS) tools have been proposed to alleviate the burden of hand-crafting approximate circuits by automating the exploitation of AC techniques. However, such tools are typically tied to a specific approximation technique or a difficult-to-extend set of techniques whose exploitation is not fully automated or steered by optimization targets. Therefore, available AHLS tools overlook the benefits of expanding the design space by mixing diverse approximation techniques toward meeting specific design objectives with minimum error. In this work, we propose an AHLS design methodology for fpgas that automatically identifies efficient combinations of multiple approximation techniques for different applications and design constraints. Compared to single-technique approaches, decreases of up to 30% in mean squared error and absolute increases of up to 6.5% in percentage accuracy were obtained for a set of image, video, signal processing and machine learning benchmarks.

关键词： High-level synthesis approximate computing field-programmable gate array design space exploration

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Performance Estimation and Prototyping of reconfigurable Near-Memory computing Systems 33

Performance Estimation and Prototyping of Reconfigurable Nea...

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33rd International conference on Field-Programmable Logic and applications (FPL)

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany German Univ Cairo Dept Elect IES Lab Cairo Egypt Tech Univ Darmstadt Darmstadt Germany Ctr Scalable Data Analyt & Artificial Intelligenc Leipzig Germany

ISBN: (纸本)9798350341515

The concept of near-memory computing (NMC) has emerged as a promising solution to address the memory wall challenges faced by future computing architectures. By utilizing modern systems that integrate 3D-stacked DRAM memory, the NMC paradigm minimizes unnecessary data movement between the memory subsystem and the CPU. FPGA vendors have incorporated 3D-stacked memories into their products to meet the increasing bandwidth requirements of memory-intensive applications, enabling fpgas to compete with GPU solutions in terms of speed and energy efficiency. Recent NMC proposals focus on different data processing workloads, including graph processing and machine learning. This work addresses the research questions of how to leverage the full bandwidth of 3D-stacked high-bandwidth memory and how to facilitate the adoption of the near-memory computing paradigm.

关键词： High bandwidth memories Near memory computing Parallel Architectures Prediction

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CYNQ: Speeding Up FPGA applications With Simplicity 31

CYNQ: Speeding Up FPGA Applications With Simplicity

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31st conference on Electronics Circuits and Systems

作者： Leon-Vega, Luis G. Avila-Torres, Diego Leon-Vega, Indra Castro-Godinez, Jorge Univ Trieste Math Informat & Geosci Dept Trieste Italy Univ Estatal Distancia Informat Sch Liberia Costa Rica Inst Tecnol Costa Rica Sch Ind Design Engn Cartago Costa Rica Inst Tecnol Costa Rica Sch Elect Engn Cartago Costa Rica

ISBN: (纸本)9798350377217;9798350377200

fpgas for hardware acceleration face several issues in their adoption by the emerging AI embedded software community, mainly due to the difficulty of getting started in the field. To address these issues, FPGA vendors have tried to simplify and combine workflows to make them user-friendly. This has also impacted the runtime libraries used on Linux to allow user space applications to interact with FPGA programmable logic. However, this approach can result in suboptimal results, given the added overhead in single-purpose applications in an attempt to generalise the runtime libraries. This work presents CYNQ Runtime Library, a simplistic and API-agnostic C/C++ runtime library with the ease of PYNQ and the efficiency of C++ and XRT. In comparison to most popular runtime libraries for AMD fpgas, our work outperforms PYNQ and XRT with more than 5.34x speedup in execution latency and more than 1.20x in large workloads than XRT, which poses a better scenario for high-performance single-purpose applications.

关键词： Field Programmable Gate Arrays Hardware Acceleration Edge computing Cloud computing High Performance computing

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reconfigurable FPGA Architectures: A Survey and applications

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Journal of The Institution of Engineers (India): Series B 2021年第1期102卷 143-156页

作者： Babu, Praveenkumar Parthasarathy, Eswaran Department of Electronics and Communication Engineering Faculty of Engineering and Technology SRM Institute of Science and Technology Kattankulathur ChennaiTamil Nadu603203 India

reconfigurable computing is a potential paradigm which has been effectively performing mostly in the developments of devices likely Field Programmable Gate Arrays (fpgas). This paper illustrates the reconfigurable architecture of FPGA and its types. Most widely used high-speed computation fabrics utilized in reconfigurable computing are fpgas. This paper demonstrates the architectures used in reconfigurable computing and shows the various advantages of using reconfigurable computing design over conventional Application-Specific Integrated Circuits for achieving high level of performance for a desired application. The survey deals with the architecture of fpgas and their types in detail. This paper also explains the highlights and challenges of fine-grained and coarse-grained architectures. fpgas have supported partial reconfiguration over the few years. This survey also includes the partial reconfiguration techniques and the various applications of reconfigurability. © 2020, The Institution of Engineers (India).

关键词： reconfigurable architectures

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REMPRO: reconfigurable Modular Processor 21

REMPRO: Reconfigurable Modular Processor

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21st ACM International conference on computing Frontiers, CF 2024

作者： Vacca, Eleonora Strollo, Elio Azimi, Sarah Dipartimento di Automatica e Informatica Politecnico di Torino Turin Italy Anzio Italy

ISBN: (纸本)9798400704925

In space applications, the electronic systems that drive mission-critical operations face unique challenges due to harsh environments characterized by temperature variations and cosmic radiation. The reliability and resilience of electronic systems become paramount in ensuring the success of space missions, where the slightest hardware failure can have profound consequences. To address these challenges, this paper introduces REMPRO, a robust processing system designed specifically for space applications. REMPRO's architecture embodies modularity at both the system and device levels, utilizing multiple chained Field-Programmable Gate Arrays (fpgas), each equipped with a triple modular redundancy (TMR) processor to enhance reliability and fault tolerance. The system is distinguished by having only one active device at a time and the ability to reconfigure autonomously in case of faults, transferring the current state to the subsequent processor to ensure continuity in mission execution and consequently enhance overall system availability. © 2024 Owner/Author.

关键词： Fault tolerance

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Dynamic Security Management of Systems on Chip via Embedded FPGA in 22nm CMOS technology 67

Dynamic Security Management of Systems on Chip via Embedded ...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Elgendy, Elsayed Ghonem, Ahmed Zaky Abouzeid, Sherif Elsadek, Islam Kevin, Liao Vincent, Yen Yap, K. C. Faith, Brian Tawfik, Eslam Yahya Ohio State Univ Columbus OH 43210 USA QuickL Corp San Jose CA USA

ISBN: (纸本)9798350387186;9798350387179

There has been a rising demand for more efficient and secure processing on the edge to cope with the number of emerging Internet of Things (IoT) applications. These applications scale from low-duty cycles high-performance tasks to high-duty cycle ultralow power operations. Embedded fpgas (efpgas) can address many of these demands given their flexibility compared to ASIC, low latency, and lower energy consumption compared to CPUs. efpgas allow for post-silicon manufacturing patch-ability, adaptive performance, and on-chip control of large SoCs. This paper presents the implementation of eFPGA tailored for secure, efficient, and flexible System-On-Chip (SoC) management. The eFPGA acts as the heart of a Security Management Unit (SMU), which is part of a larger secure SoC platform that combines a True Random Number Generator (TRNG), an AES engine, and a NIST-compliant Lightweight cryptographic engine (LWC). Fabricated on 22nm CMOS technology, the eFPGA was used to dynamically manage the security policies of different IPs in the SoC under a proposed threat model. We report the performance of these applications, showing the benefits the embedded fabric provides.

关键词： Embedded FPGA SoC Security Security Policy Management reconfigurable computing System on a Chip

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