检索结果-内蒙古大学图书馆

20th ACM International conference on computing Frontiers (CF)

作者： Mika, Kevin Griessl, Rene Kucza, Nils Porrmann, Florian Kaiser, Martin Tigges, Lennart Hagemeyer, Jens Trancoso, Pedro Azhar, Muhammad Waqar Qararyah, Fareed Zouzoula, Stavroula Menetrey, James Pasin, Marcelo Felber, Pascal Marcus, Carina Brunnegard, Oliver Eriksson, Olof Salomonsson, Hans Odman, Daniel Ask, Andreas Casimiro, Antonio Bessani, Alysson Carvalho, Tiago Gugala, Karol Zierhoffer, Piotr Latosinski, Grzegorz Tassemeier, Marco Porrmann, Mario Heyn, Hans-Martin Knauss, Eric Mao, Yufei Meierhoefer, Franz Bielefeld Univ Bielefeld Germany Chalmers Univ Technol Gothenburg Sweden Univ Neuchatel Neuchatel Switzerland VEONEER Inc Vargarda Sweden EMBEDL AB Gothenburg Sweden Univ Lisbon Lisbon Portugal Antmicro Poznan Poland Osnabruck Univ Osnabruck Germany Univ Gothenburg Gothenburg Sweden Siemens AG Erlangen Germany

ISBN: (纸本)9798400701405

The VEDLIoT project aims to develop energy-efficientDeep Learning methodologies for distributed Artificial Intelligence of Things (AIoT) applications. During our project, we propose a holistic approach that focuses on optimizing algorithms while addressing safety and security challenges inherent to AIoT systems. The foundation of this approach lies in a modular and scalable cognitive IoT hardware platform, which leverages microserver technology to enable users to configure the hardware to meet the requirements of a diverse array of applications. Heterogeneous computing is used to boost performance and energy efficiency. In addition, the full spectrum of hardware accelerators is integrated, providing specialized ASICs as well as fpgas for reconfigurable computing. The project's contributions span across trusted computing, remote attestation, and secure execution environments, with the ultimate goal of facilitating the design and deployment of robust and efficient AIoT systems. The overall architecture is validated on use-cases ranging from Smart Home to Automotive and Industrial IoT appliances. Ten additional use cases are integrated via an open call, broadening the range of application areas.

关键词： Artificial Intelligence of Things (AIoT) Acceleration reconfigurable and Heterogeneous computing Machine Learning (ML) Distributed Attestation and Security

来源：评论

学校读者我要写书评

暂无评论

SmartFuse: reconfigurable Smart Switches to Accelerate Fused Collectives in HPC applications 24

SmartFuse: Reconfigurable Smart Switches to Accelerate Fused...

引用

38th ACM International conference on Supercomputing (ACM ICS)

作者： Haghi, Pouya Tan, Cheng Guo, Anqi Wu, Chunshu Liu, Dongfang Li, Ang Skjellum, Anthony Geng, Tong Herbordt, Martin Univ Rochester Rochester NY 14627 USA Microsoft Redmond WA USA Boston Univ Boston MA 02215 USA Rochester Inst Technol Rochester NY 14623 USA Tennessee Technol Univ Cookeville TN 38505 USA

ISBN: (纸本)9798400706103

Communication switches have sometimes been augmented to process collectives, e.g., in the IBM BlueGene and Mellanox SHArP switches. In this work, we find that there is a great acceleration opportunity through the further augmentation of switches to accelerate more complex functions that combine communication with computation. We consider three types of such functions. The first is fully-fused collectives built by fusing multiple existing collectives like Allreduce with Alltoall. The second is semi-fused collectives built by combining a collective with another computation. The third are higher-order collectives built by combining multiple computations and communications, such as to perform matrix-matrix multiply (PGEMM). In this work, we propose a framework called SmartFuse to accelerate fused collective functions. The core of SmartFuse is a reconfigurable smart switch to support these operations. The semi/fully fused collectives are implemented with a CGRA-like architecture, while higher-order collectives are implemented with a more specialized computational unit that can also schedule communication. Supporting our framework is software to evaluate and translate relevant parts of the input program, compile them into a control data flow graph, and then map this graph to the switch hardware. The proposed framework, once deployed, has the strong potential to accelerate existing HPC applications transparently by encapsulation within an MPI implementation. Experimental results show that this approach improves the performance of the PGEMM kernel, miniFE, and AMG by, on average, 94%, 15%, and 13%, respectively.

关键词： In-Switch computing High Performance computing fpgas

来源：评论

学校读者我要写书评

暂无评论

A Dynamically reconfigurable Single-Board Computer for High Dynamic Range Space Cameras 10

A Dynamically Reconfigurable Single-Board Computer for High ...

引用

10th International conference on Space Mission Challenges for Information technology

作者： Guerrieri, Andrea Rodriguez-Martinez, David Charbon, Edoardo HES SO Valais Wallis Sch Engn Sion Switzerland EPFL Adv Quantum Architecture Lab AQUA Neuchatel Switzerland

ISBN: (纸本)9798350384529;9798350384512

In response to a growing demand for autonomous in-orbit operations and the pressing need for these operations to take place in an ever-widening set of environmental conditions, significant advancements have been made in the miniaturization and improvement of space-qualified sensing instrumentation. Yet, the effectiveness of vision-driven autonomous operations relies heavily on cameras with superior low-light performance and dynamic range, for which an optimal solution is yet to be found. Single-Photon Avalanche Diode (SPAD) sensors emerge as a potential solution, offering high light sensitivity and dynamic range even with diminutive pixel sizes. However, their high bandwidth and efficient integration with single-board computers requires bespoke interfaces and real-time processing power, typically enabled by Field Programmable Gate Arrays (fpgas). This paper presents a dynamically reconfigurable onboard computer designed for efficient data processing and seamless integration into the first space-qualified camera leveraging a 1-megapixel SPAD sensor. Future endeavors entail developing a demonstrator capable of acquiring exceptionally sharp and high dynamic range imagery under some of the most complex illumination conditions found in space. This paper outlines the technological advancements and a roadmap toward revolutionizing spacecraft imaging capabilities, paving the way for enhanced image acquisition and data processing in time-sensitive, autonomous space operations.

关键词： reconfigurable computing SPAD Sensors HDR Space Camera

来源：评论

学校读者我要写书评

暂无评论

Optimizing Tactile Feedback Devices with Fixed-Point Computation on FPGA

引用

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年第6期44卷 3826-3864页

作者： Junior, Jose C. V. S. Balza, Micael Silva, Sergio N. da Silva, Lucileide M. D. Fernandes, Marcelo A. C. Fed Univ Rio Grande do Norte UFRN InovAI Lab nPITI IMD BR-59078900 Natal RN Brazil Univ Fed Rio Grande do Norte Leading Adv Technol Ctr Excellence LANCE nPITI IMD BR-59078900 Natal RN Brazil Fed Inst Educ Sci & Technol Rio Grande do Norte IF BR-59200000 Santa Cruz RN Brazil Univ Fed Rio Grande do Norte Dept Comp & Automat Engn BR-59078900 Natal RN Brazil

This article targets the implementation of a bilateral control algorithm for haptic devices on FPGA platforms, using fixed-point arithmetic (FxP-F) to overcome latency and processing efficiency challenges. The results show significant improvements in processing speed and latency reduction, with an efficient implementation that leverages the flexibility and parallelism of fpgas. Compared to current technologies, the proposed solutions offer superior performance, with a notable increase in the sampling rate, which results in greater haptic fidelity. These contributions not only significantly advance the field of haptic technology but also pave new paths for applications in virtual reality, teleoperation, and other domains that require precise and responsive remote tactile interaction. This study establishes a new benchmark for developing low-latency, high-performance haptic systems, promising to improve how we interact with virtual and remote environments.

关键词： Haptic device Teleoperation control algorithm reconfigurable hardware Parallel computing FPGA

来源：评论

学校读者我要写书评

暂无评论

A hardware acceleration Framework of reconfigurable Edge Modules for Convolutional Neural Networks 50

A hardware acceleration Framework of Reconfigurable Edge Mod...

引用

50th Annual conference of the IEEE Industrial Electronics Society, IECON 2024

作者： Qiao, Yiming Jia, Zidi Li, Shixiang Ren, Lei Beihang University Beijing China Beihang University Zhongguancun Laboratory State Key Laboratory of Intelligent Manufacturing System Technology Beijing China

ISBN: (纸本)9781665464543

Edge computing exploits node devices situated in close proximity to terminals to deliver distributed computing services directly to users, with fpgas serving as the predominant platform. With the amplification in volume and intricacy of deep learning models, effectively deploying these models on FPGA devices introduces substantial challenges. To counter this predicament, this paper introduces an FPGA-based hardware acceleration framework for reconfigurable edge devices tailored for Convolutional Neural Networks (CNNs). Initially, a method for dynamically quantizing network models is devised to markedly curtail model memory consumption. Subsequently, a meticulously engineered hardware acceleration unit is formulated to attain augmented computing parallelism via meticulous temporal redesign. Finally, model deployment on FPGA devices for inference verification is showcased utilizing fully connected and convolutional neural networks as exemplars. On the MNIST dataset, the FPGA inference unit attains remarkable accuracy and computational efficiency in comparison to CPUs and GPUs. © 2024 IEEE.

关键词： Convolutional neural networks

来源：评论

学校读者我要写书评

暂无评论

An Optimized Topology for High-Performance reconfigurable computing. Part I: Analysis of 2D and 3D NoC Topologies

An Optimized Topology for High-Performance Reconfigurable Co...

引用

2023 IEEE International conference on Emerging Trends in Engineering, Sciences and technology, ICES and T 2023

作者： Ijaz, Qaiser Bourennane, El-Bay University of Burgundy ImViA Laboratory Dijon France

ISBN: (纸本)9781665455602

With a pledge to improve the performance per watt, fpgas have earned a place in the world's leading center for high-performance computing, which has opened new avenues for research. In pursuit of an optimized topology in the context of reconfigurable computing, we analyzed six selected 2D and 3D NoC topologies. The results showed that the 3D Torus demonstrated significant throughput as network size, the number of nodes transferring messages, and message size varied. Based on performance analysis and anticipated acceptable resource utilization, we singled out the 3D Torus for further investigation and optimization. © 2023 IEEE.

关键词： Topology

来源：评论

学校读者我要写书评

暂无评论

End-to-end codesign of Hessian-aware quantized neural networks for fpgas

引用

ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2024年第3期17卷 1-22页

作者： Campos, Javier Mitrevski, Jovan Tran, Nhan Dong, Zhen Gholaminejad, Amir Mahoney, Michael W. Duarte, Javier Fermilab Natl Accelerator Lab Batavia IL 60510 USA Univ Calif Berkeley Berkeley CA USA Univ Calif San Diego La Jolla CA USA

We develop an end-to-end workflow for the training and implementation of co-designed neural networks quantization of NNs, the Quantized Open Neural Network Exchange intermediate representation, and the hls4ml tool flow for transpiling NNs into FPGA firmware. This makes efficient NN implementations in hardware accessible to nonexperts in a single open sourced workflow that can be deployed for real-time machinelearning applications in a wide range of scientific and industrial settings. We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40-MHz collision rate of the CERN Large Hadron Collider (LHC). Given the high collision rate, all data processing must be implemented on FPGA hardware within the strict area and latency requirements. Based on these constraints, we implement an optimized mixed-precision NN classifier for high-momentum particle jets in simulated LHC proton-proton collisions.

关键词： CCS Concepts Networks- Network algorithms Data path algorithms computing methodolo- gies- Neural networks Hardware- Hardware accelerators

来源：评论

学校读者我要写书评

暂无评论

A Dynamic Logic Based reconfigurable Digital CIM Macro for Edge computing 6

A Dynamic Logic Based Reconfigurable Digital CIM Macro for E...

引用

6th International conference on Circuits and Systems

作者： Hao, Yingbo Chen, Huangxu Zou, Yi Yang, Yanfeng South China Univ Technol Sch Microelect Guangzhou Peoples R China

ISBN: (纸本)9798350352153;9798350352160

The imperative for energy efficiency in Artificial Intelligence (AI) aligns with global environmental sustainability goals, presenting substantial challenges. Compute-in-memory (CIM) offers a viable solution for edge computing, capitalizing on its superior energy efficiency and bandwidth. Yet, the specialized nature of CIM hardware impedes its broader adoption in AIoT applications. This study introduces a dynamically reconfigurable digital CIM leveraging dynamic logic to enhance energy efficiency. Dynamic logic reduces transistor count and transmission delay compared to static logic, thereby augmenting the energy efficiency ratio. It features a reconfigurable Manchester carry chain for adaptable computation across different data bit-widths and incorporates reusable computation units supporting seven operator types, minimizing circuit area. Evaluation using TSMC 40-nm CMOS technology demonstrates that the proposed macro circuit operates at 800 MHz at 1.1 V, achieving energy efficiencies of 0.76 TOPS/W for 8-bit multiplication and 4.22 TOPS/W for 8-bit addition at 0.8 V. Emulation of neural networks (NNs) within the AIoT framework demonstrates that a significant number of computational cycles can be executed using a minimal set of instructions.

关键词： Compute-in-memory (CIM) Dynamic Logic SRAM reconfigurable Artificial Intelligence (AI) Accelerator

来源：评论

学校读者我要写书评

暂无评论

20th International Symposium on Applied reconfigurable computing, ARC 2024

20th International Symposium on Applied Reconfigurable Compu...

引用

20th International Symposium on Applied reconfigurable computing, ARC 2024

ISBN: (纸本)9783031556722

The proceedings contain 21 papers. The special focus in this conference is on Applied reconfigurable computing. The topics include: Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training;reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach;Bridging the Gap in ECG Classification: Integrating Self-supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware Constraints;Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance computing;LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization;cryptographic Security Through a Hardware Root of Trust;analysis of Clock Tree Buffer Degradation Caused by Radiation;NEUROSEC: FPGA-Based Neuromorphic Audio Security;Secure eFPGA Configuration: A System-Level Approach;Graphtoy: Fast Software Simulation of applications for AMD’s AI Engines;A DSL and MLIR Dialect for Streaming and Vectorisation;Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices;high Performance Connected Components Accelerator for Image Processing in the Edge;Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator;trusted computing Architectures for IoT Devices;PROACT - Physical Attack Resistance of Cryptographic Algorithms and Circuits with Reduced Time to Market;A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed computing;A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator;Exploiting fpgas and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Accelerating Deep Neural Network-Based Image Analysis Using reconfigurable Architecture 4th

Accelerating Deep Neural Network-Based Image Analysis Using ...

引用

4th International conference on Frontiers in computing and Systems, COMSYS 2023

作者： Pal, Ranita Ganguly, Prapti Bhattacharjee, Shuvadeep Mandal, Swagata Chakrabarti, Amlan Chatterjee, Sayan Jadavpur University West Bengal Kolkata India A.K. Choudhury School of Information Technology University of Calcutta West Bengal Kolkata India Jalpaiguri Government Engineering College West Bengal Jalpaiguri India

ISBN: (纸本)9789819726134

This study explores the utilization of reconfigurable architectures, specifically field-programmable gate arrays (fpgas), for accelerating image classification tasks based on deep neural networks (DNNs). The COVID-19 Radiography Database, consisting of COVID-19 chest X-ray images, is analyzed using three different DNN classification model architectures. The trained model weights are compiled for hardware-specific execution on an FPGA board, taking advantage of the parallel processing capabilities and hardware acceleration offered by the DPU architecture. Performance in terms of the accuracy of the model is evaluated along with inference time and resource utilization. The experimental results demonstrate significant improvements in speed and energy efficiency through the integration of software and hardware components. The findings provide valuable insights into the potential of Field Programmable Gate Array (fpgas) and Deep Learning Processing Units (DPUs) in enhancing image analysis tasks based on deep neural networks, paving the way for future advancements in this field. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Deep neural networks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：