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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

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FPGA-based Accelerator for FFT-Processing in Edge computing 12

FPGA-based Accelerator for FFT-Processing in Edge Computing

引用

12th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems: technology and applications, IDAACS 2023

作者： Schulz, Peter Sleahtitchi, Grigore Haw Hamburg HamburgD-20099 Germany

ISBN: (纸本)9798350358056

Edge computing bridges the gap between end devices on the Internet of Things (IoT) and central, server-based IT services by accelerating tasks which otherwise could not be executed on the IoT device itself. The Fast Fourier Transformation (FFT) is used as an example for the arithmetic tasks to be supported. To support such specific applications, we envisage a concept for edge computing in which co-processing is implemented using Field Programmable Gate Arrays (fpgas). This article first describes certain edge computing requirements using the example of moving drones. This involves the case-by-case reconfiguration of the computation hardware and a handover mechanism from one edge node to another. Then follows the description of an FPGA-based FFT accelerator unit and its extension to an FFT co-processor. The development took place under the proviso that, for example, drones can request different co-processors and that the drones can also change the edge node when changing a radio cell, which results in a handover of the co-processor context. Regarding the FPGA part this means that the co-processor is part of a partially reconfigurable environment, and the co-processor must support the handover mechanisms in terms of hardware. Finally, the need for FPGA resources is analyzed, also in comparison with alternative solutions. © 2023 IEEE.

关键词： Edge computing FFT FPGA partitial FPGA reconfiguration

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High accuracy, fully reconfigurable DAQ system for sensing temperature 33

High accuracy, fully reconfigurable DAQ system for sensing t...

引用

33rd International Scientific conference Electronics, ET 2024

作者： Gatev, Vasil D. Mollov, Valentin S. Petrov, Panayot L. Manoeva, Mariana D. Technical University of Sofia Faculty of Computer Systems and Technologies Department of Computer Systems 8 Kliment Ohridski blvd. Sofia1000 Bulgaria Technical University of Sofia Faculty of Electronic Engineering and Technologies Department of Electronics 8 Kliment Ohridski blvd. Sofia1000 Bulgaria

ISBN: (纸本)9798350376449

The FPGA configurable integrated circuits (ICs) are a valid alternative to the common microcontroller solutions for application-specific (ASIC) embedded applications. The fpgas are applied in the prototype step, before the ASIC synthesis, for end-user devices targeted to real-time applications. Nowadays IoT solutions with post-processing on cloud-based server technology, makes the dedicated DAQ device an important component in the system. The fpgas are the appropriate basis for such device, where the data acquisition of analog values and its transfer to digital representation must be achieved with high-speed, high-resolution, low power consumption and effective optimization of the IC resources. © 2024 IEEE.

关键词： Application specific integrated circuits

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AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous reconfigurable computing Platform Versal ACAP 42

AIM: Accelerating Arbitrary-precision Integer Multiplication...

引用

42nd IEEE/ACM International conference on Computer-Aided Design (ICCAD)

作者： Yang, Zhuoping Zhuang, Jinming Yin, Jiaqi Yu, Cunxi Jones, Alex K. Zhou, Peipei Univ Maryland College Pk MD 20742 USA Univ Pittsburgh Pittsburgh PA 15260 USA

ISBN: (纸本)9798350322255

Arbitrary-precision integer multiplication is the core kernel of many applications including scientific computing, cryptographic algorithms, etc. Existing acceleration of arbitrary-precision integer multiplication includes CPUs, GPUs, fpgas, and ASICs. To leverage the hardware intrinsics low-bit function units (32/64-bit), arbitrary-precision integer multiplication can be calculated using Karatsuba decomposition, and Schoolbook decomposition by decomposing the two large operands into several small operands, generating a set of low-bit multiplications that can be processed either in a spatial or sequential manner on the low-bit function units, e.g., CPU vector instructions, GPU CUDA cores, FPGA digital signal processing (DSP) blocks. Among these accelerators, reconfigurable computing, e.g., FPGA accelerators are promised to provide both good energy efficiency and flexibility. We implement the state-of-the-art (SOTA) FPGA accelerator and compare it with the SOTA libraries on CPUs and GPUs. Surprisingly, in terms of energy efficiency, we find that the FPGA has the lowest energy efficiency, i.e., 0.29x of the CPU and 0.17x of the GPU with the same generation fabrication. Therefore, key questions arise: Where do the energy efficiency gains of CPUs and GPUs come from? Can reconfigurable computing do better? If can, how to achieve that? We first identify that the biggest energy efficiency gains of the CPUs and GPUs come from the dedicated vector units, i.e., vector instruction units in CPUs and CUDA cores in GPUs. FPGA uses DSPs and lookup tables (LUTs) to compose the needed computation, which incurs overhead when compared to using vector units directly. New reconfigurable computing, e.g., "FPGA+vector units" is a novel and feasible solution to improve energy efficiency. In this paper, we propose to map arbitrary-precision integer multiplication onto such a "FPGA+vector units" platform, i.e., AMD/Xilinx Versal ACAP architecture, a heterogeneous reconfigurable computing pla

关键词： Heterogeneous reconfigurable computing architecture Versal ACAP mapping framework arbitrary-precision integer computing

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A Dynamic Partial reconfigurable CGRA Framework for Multi-Kernel applications 22

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Ke...

引用

22nd International conference on Field Programmable technology (ICFPT)

作者： Zhu, Qilong Cao, Yuhang Qiu, Yunhui Gao, Xuchen Yin, Wenbo Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9798350359114

When an application is accelerated with CoarseGrained reconfigurable Architecture (CGRA), it is compiled into Data Flow Graph (DFG). In conventional CGRA frameworks, only one DFG is accelerated in each epoch. Consequently, singlecontext CGRAs can't fully utilize hardware resources when executing multi-kernel applications. In this paper, we propose a dynamic partial reconfigurable CGRA framework for multikernel applications. The modeled CGRA can flexibly partition hardware resources and support parallelism of multiple DFGs by implementing dynamic partial reconfiguration (DPR). A multikernel scheduler based on integer linear programming (ILP) makes a timetable for the execution state of the application, and an incremental mapper compiles DFGs according to the timetable. Compared with the baseline, TRAM, our framework achieves an average throughput increase of 67.30% and utilization increase of 32.46% for a single task with multikernels while an average execution time reduction of 55.71% and an average utilization increase of 70.43% for applications with multiple tasks.

关键词： dynamic partial reconfiguration CGRA parallel computing multi tasks schedule

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Slotted Meander reconfigurable Antenna for 5G Application 5

Slotted Meander Reconfigurable Antenna for 5G Application

引用

5th International conference on Circuits, Control, Communication and computing, I4C 2024

作者： Rakshitha, R. Prabhakar, Parimala Naik, Saipriya Krishna Gowda, Kishan B Tauheed, Mohammed Ramaiah Institute of Technology Department of Electronics and Telecommunication Bengaluru India

ISBN: (纸本)9798331528539

This project involves the design and implementation of a reconfigurable antenna system tailored explicitly to 5G applications. The proposed slotted meander reconfigurable patch antenna for 5G communication has been designed with dimensions of 27.25 mm × 32.94 mm × 0.03 mm and features a non-uniform slotted meander configuration. The impedance matching and radiation characteristics of the antenna are greatly improved by these slots. The antenna is excited through a linear feeding technique and has been fabricated on a compact size of 42mmtimes 42mm with 1.575mm thick Rogers 5880 substrate. Designed antenna achieves a bandwidth below -15 dB in the range of 3.8 GHz to 5.5 GHz, encompassing the globally authorized FR1 spectrum. In addition to this, the antenna results in gain of 6.7dB and 4.9dB for the center frequency of 5.44 and 3.86 GHz. The proposed antenna's compact size and strong performance make it an ideal choice for 5G applications. The design aims to simulate and test optimized 5G use case antennas capable of dynamically reconfiguring operational parameters like frequency, polarization, or radiation pattern for real-time optimum performance, with the design and simulations conducted using HFSS software and results obtained accordingly. © 2024 IEEE.

关键词： 5G mobile communication systems

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A Hardware Virtualization Scheme for reconfigurable Service Providing in the Internet of Things Era

A Hardware Virtualization Scheme for Reconfigurable Service ...

引用

2024 IEEE URUCON, URUCON 2024

作者： Castro, Eddie Muñoz, Daniel Yudi, Jones University of Brasilia Brasilia Brazil

ISBN: (纸本)9798350355383

With the emergence of the Internet of Things, there is a growing demand for distributed and federated processing in consortium with several devices. One current trend is to use devices as processing hubs, providing services such as Software as a Service, Hardware as a Service and Storage as a Service. In this context, reconfigurable computing with Field-Programmable Gate Arrays (fpgas) brings a new perspective since modern devices have hardware/software flexibility to change their behaviour according to the application. A Hardware as a Service (HaS) scheme for hardware virtualization is necessary to support the different demands. Integrating software applications with FPGA implementations via their physical interfaces (IO) poses considerable challenges, hindering the integration of software and hardware solutions. This paper introduces a software architecture paired with FPGA technology to establish an isolated, decoupled, and scalable testing environment. The proposed methodology and its implementation demonstrate the efficacy of this approach in facilitating rapid prototyping and deployment. The results indicate successful integration with minimal development effort. © 2024 IEEE.

关键词： Application programs

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Real-time Independent Components Analysis for Dimensional Reduction of Hyperspectral Images Using reconfigurable Hardware 26

Real-time Independent Components Analysis for Dimensional Re...

引用

26th Euromicro conference on Digital System Design (DSD) / 49th Euromicro conference on Software Engineering and Advanced applications (SEAA)

作者： Fernandez, Daniel Gonzalez, Carlos Mozos, Daniel Univ Complutense Madrid Madrid Spain

ISBN: (纸本)9798350344196

Hyperspectral image analysis represents an extremely complex procedure from a computational point of view, mainly due to the high dimensionality of the data. This computational cost represents a significant disadvantage in applications that require a real-time response, such as fire monitoring, prevention and monitoring of natural disasters, chemical spills, and other environmental pollutants. Dimensional reduction allows us to decrease the size of the image while preserving the important discriminating features, by eliminating redundant data or noise. Due to their reduced size, weight, and power consumption when compared to other high-performance computing systems, reconfigurable hardware solutions, such as field-programmable gate arrays, have been consolidated in recent years as one of the standard options for the quick processing of hyperspectral remotely sensed images. In this paper, we have implemented an optimized hardware version of the Fast Independent Component Analysis (FastICA) version for dimensional reduction of hyperspectral images using an FPGA device. Our implementation achieves a 34x speedup compared with its equivalent software version, achieving the objective of real-time processing considering the capture time of the AVIRIS spectral sensor.

关键词： Hyperspectral imaging dimensional reduction fast independent component analysis (FastICA) reconfigurable hardware field-programmable gate arrays (fpgas)

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A reconfigurable Dataflow Baseband Processor for MIMO Communication System applications 9

A Reconfigurable Dataflow Baseband Processor for MIMO Commun...

引用

9th International conference on Integrated Circuits and Microsystems, ICICM 2024

作者： Song, Zikang Wu, Haibin Fan, Dongrui School of Microelectronics University of Science and Technology of China Hefei China Institute of Computing Technology Chinese Academy of Sciences State Key Lab of Processors Beijing China

ISBN: (纸本)9798331509453

Multiple-Input Multiple-Output (MIMO) technol-ogy is extensively used in various communication scenarios, posing challenges to the flexibility and real-time performance of its hardware solutions. In this paper, we propose a reconfigurable dataflow baseband processor which can flexibly deploy and efficiently execute operators extracted from MIMO communication system using dataflow graphs. Experimental results demonstrate that the proposed design offers high flexibility and strong real-time performance. Additionally, it achieves 2.38×and 1.80× improvement in energy efficiency compared to similar reconfig-urable architecture and ASIC, respectively, with an antenna size of 128×8. © 2024 IEEE.

关键词： reconfigurable architectures

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Design and Development of an FPGA-Based Real-Time reconfigurable computing Platform

Design and Development of an FPGA-Based Real-Time Reconfigur...

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NIELIT's International conference on Communication, Electronics and Digital technology, NICE-DT 2023

作者： Kidav, Jayaraj U. Mohan, Varun National Institute of Electronics and Information Technology Kerala Calicut India

ISBN: (纸本)9789819916986

The computational requirements in modern workloads like artificial intelligence (AI), machine learning (ML), etc., demand the necessity of hardware acceleration and partial reconfiguration (PR) on a platform like a field programmable gate array (FPGA). In this work, the extendibility and modularity of reduced instruction set computer (RISC)-V® instruction set architecture (ISA) are combined with the dynamic partial reconfigurable features of contemporary fpgas, to develop new hardware accelerated computing architecture. The architecture executes the extended instruction as a coprocessor implementation, and the necessary coprocessor logic will be loaded into the PR region in real time. The work also explores the idea of having multiple PR regions and caching frequently used coprocessor logic and evaluates its impact on system performance. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Coprocessor

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Migration of GPU applications from CUDA to SYCL Programming Model 8

Migration of GPU Applications from CUDA to SYCL Programming ...

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8th IEEE International conference on Computational System and Information technology for Sustainable Solutions, CSITSS 2024

作者： Narayan Gaur, Yogesh Khanna, Manju Amrita School of Computing Amrita Vishwa Vidyapeetham Department of Computer Science & Engineering Bengaluru India

ISBN: (纸本)9798331505462

Due to new enhancements in the field of computer architecture and the proliferation of heterogeneous computing devices, there is an increasing demand for portable and efficient programming applications. These applications are essential for harnessing the capabilities of diverse hardware devices found on heterogeneous platforms, which include CPUs, GPUs, NPUs, and fpgas from different hardware vendors like Intel, Nvidia, and AMD. CUDA-based applications are designed exclusively for execution on Nvidia GPUs, whereas the SYCL standard, combining modern C++ features, allows single-source code to operate on heterogeneous computing devices. This study compares the SYCL and CUDA programming interfaces and provides concepts and guidance on migrating CUDA-based applications to the SYCL interface covering aspects like memory management, kernel launch, execution hierarchy, synchronization, debugging etc. across both programming models. Study also underscores the potential of the SYCL programming interface as a practical solution for attaining both portability and performance in the modern computing systems, particularly across heterogeneous devices, with case-study covering migration of CUDA model-based vector addition code to the SYCL model. © 2024 IEEE.

关键词： C++ (programming language)

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