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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是51-60 订阅

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Analysis and application on enhancing CNN performance via FPGA integration

Analysis and application on enhancing CNN performance via FP...

引用

2024 International conference on Electronics, Electrical and Information Engineering, ICEEIE 2024

作者： Zhu, Yihang School of Integrated Circuits Guangdong University of Technology Guangzhou China

ISBN: (数字)9781510686809

ISBN: (纸本)9781510686793

In the rapidly advancing realm of information processing, the intersection of Field Programmable Gate Array (FPGA) technology and Convolutional Neural Networks (CNNs) has garnered considerable attention. This paper presents a comprehensive review of the evolution of fpgas and CNNs, delving into the architectural intricacies of fpgas and the compositional elements of CNNs, encompassing the convolutional layer, pooling layer, and fully connected layer. A particular emphasis is placed on analyzing the principles and functionality of the pipeline structure in fpgas, elucidating its pivotal role in expediting the CNN inference process. The integration of pipeline architecture within fpgas is a strategic design choice aimed at enhancing data processing efficiency. This structure allows for the execution of instructions across multiple stages concurrently, significantly boosting computational speed, a feature particularly advantageous for the extensive matrix operations characteristic of convolutional neural networks. Concurrently, CNNs have emerged as a powerhouse in deep learning, demonstrating remarkable success in image recognition and speech processing domains. These networks function by extracting features through sequential layer processing and executing classifications in the fully connected layer. When juxtaposed with traditional CPUs and GPUs, fpgas reveal distinct benefits in CNN applications. The inherent programmability of fpgas permits extensive customization, aligning seamlessly with diverse neural network architectures and achieving superior energy efficiency. However, it's crucial to note that CPUs and GPUs maintain certain advantages in general-purpose computing, particularly in handling complex logic and extensive data sets. © 2024 SPIE.

关键词： Convolutional neural networks

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Heterogeneous reconfigurable Accelerators: Trends and Perspectives 60

Heterogeneous Reconfigurable Accelerators: Trends and Perspe...

引用

60th ACM/IEEE Design Automation conference (DAC)

作者： Luk, Wayne Imperial Coll Dept Comp London England

ISBN: (纸本)9798350323481

Heterogeneity and reconfigurability have both been adopted by accelerators to improve their flexibility and efficiency for a wide variety of applications, from cloud computing to embedded systems. This paper provides an overview of the trends of heterogeneous reconfigurable accelerators including fieldprogrammable gate arrays and coarse-grained reconfigurable arrays, and the related design automation approaches for enhancing design quality and designer productivity of these accelerators. We shall also discuss how recent advances in technology, such as multi-level co-design, heterogeneous Functionas-a-Service and meta-programming, would help address the challenges in engineering next-generation heterogeneous reconfigurable accelerators and beyond.

关键词： accelerator heterogeneous reconfigurable FPGA GPU CGRA

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Implementation and applications of Neural Networks Based on FPGA

Implementation and Applications of Neural Networks Based on ...

引用

2024 International conference on Electrical Drives, Power Electronics and Engineering, EDPEE 2024

作者： Li, Jiajun Zhang, Chuhuan Ma, Xiangcheng Shenzhen College Of International Education Shenzhen China Nanjing University Of Aeronautics And Astronautics Nanjing China

ISBN: (纸本)9798350395631

Deep neural networks have been crucial in several recent developments in artificial intelligence and big data technology, including natural language processing, speech recognition, and computer vision. Given the numerous layers of deep neural network models, the computational complexity, and a large number of parameters, the performance of hardware such as computing power, memory bandwidth, and data storage is highly demanding. Due to their high parallelism, low power consumption, and reconfigurability, Field Programmable Gate Arrays (fpgas), which are programmable logic devices, are frequently used as an alternative to CPUs and GPUs. Their combination with neural networks has become a current research hotspot in the field of artificial intelligence. This paper briefly describes firstly the current mainstream neural network models and the design ideas of fpgas. Next, the applications of FPGA-based neural networks are introduced. Finally, this paper concludes with a summary and outlook on the development of FPGA-based applications for deep neural networks. © 2024 IEEE.

关键词： Deep neural networks

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RO-SVD: A reconfigurable Hardware Copyright Protection Framework for AIGC applications 35

RO-SVD: A Reconfigurable Hardware Copyright Protection Frame...

引用

35th IEEE International conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Ran, Zhuoheng Abdelgawad, Muhammad A. A. Zhang, Zekai Cheung, Ray C. C. Yan, Hong City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China City Univ Hong Kong Ctr Intelligent Multidimens Data Anal Hong Kong Peoples R China

ISBN: (纸本)9798350349641;9798350349634

The dramatic surge in the utilisation of generative artificial intelligence (GenAI) underscores the need for a secure and efficient mechanism to responsibly manage, use and disseminate multi-dimensional data generated by artificial intelligence (AI). In this paper, we propose a blockchain-based copyright traceability framework called ring oscillator-singular value decomposition (RO-SVD), which introduces decomposition computing to approximate low-rank matrices generated from hardware entropy sources and establishes an AI-generated content (AIGC) copyright traceability mechanism at the device level. By leveraging the parallelism and reconfigurability of field-programmable gate arrays (fpgas), our framework can be easily constructed on existing AI-accelerated devices and provide a low-cost solution to emerging copyright issues of AIGC. We developed a hardware-software (HW/SW) co-design prototype based on comprehensive analysis and on-board experiments with multiple AI-applicable fpgas. Using AI-generated images as a case study, our framework demonstrated effectiveness and emphasised customisation, unpredictability, efficiency, management and reconfigurability. To the best of our knowledge, this is the first practical hardware study discussing and implementing copyright traceability specifically for AI-generated content.

关键词： AI-generated content copyright protection singular value decomposition (SVD) blockchain nanofabrication AI security low-power AI

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reconfigurable Distributed FPGA Cluster Design for Deep Learning Accelerators

Reconfigurable Distributed FPGA Cluster Design for Deep Lear...

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2023 IEEE International conference on Electro Information technology, eIT 2023

作者： Johnson, Hans Fang, Tianyang Perez-Vicente, Alejandro Saniie, Jafar Research Laboratory Department of Electrical and Computer Engineering ChicagoIL United States

ISBN: (纸本)9781665493765

We propose a distributed system based on low-power embedded fpgas designed for edge computing applications focused on exploring distributing scheduling optimizations for Deep Learning (DL) workloads to obtain the best performance regarding latency and power efficiency. Our cluster was modular throughout the experiment, and we have implementations that consist of up to 12 Zynq-7020 chip-based boards as well as 5 UltraScale+ MPSoC FPGA boards connected through an ethernet switch, and the cluster will evaluate configurable Deep Learning Accelerator (DLA) Versatile Tensor Accelerator (VTA). This adaptable distributed architecture is distinguished by its capacity to evaluate and manage neural network workloads in numerous configurations which enables users to conduct multiple experiments tailored to their specific application needs. The proposed system can simultaneously execute diverse Neural Network (NN) models, arrange the computation graph in a pipeline structure, and manually allocate greater resources to the most computationally intensive layers of the NN graph. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Creating an Error-Tolerant Adder for Image Processing applications Using FPGA technology 7th

Creating an Error-Tolerant Adder for Image Processing Applic...

引用

7th International conference on Soft computing and Signal Processing, ICSCSP 2024

作者： Rohith Kumar, Bairi. Niranjan Reddy, K. John Alex, E. Department of Electronics and Communication Engineering CMR Institute of Technology Hyderabad India

ISBN: (纸本)9789819799251

Image processing applications often require error-tolerant adders to ensure accurate computation despite potential hardware faults. Field-programmable gate array (FPGA) technology, coupled with very large-scale integration (VLSI) techniques, offers a versatile platform for implementing such adders. Contribution a new error-tolerant adder designed explicitly for image processing applications is proposed. Our methodology leverages the inherent reconfigurability of fpgas to dynamically adapt to changing error patterns, thereby enhancing fault tolerance. By employing redundant computing resources and error detection/correction mechanisms at various stages of the adder architecture, we mitigate the impact of transient errors and aging-related faults. To validate the effectiveness of our approach, we conduct extensive simulations and synthesis experiments using XILINX software. The results demonstrate significant improvements in error tolerance compared to conventional adder designs, making our proposed architecture well-suited for demanding image processing applications in safety–critical environments. Overall, our work contributes to advancing the state-of-the-art error-tolerant computing for FPGA-based image processing systems. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Image enhancement

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RapidOMS: FPGA-based Open Modification Spectral Library Searching with HD computing

RapidOMS: FPGA-based Open Modification Spectral Library Sear...

引用

2024 Biomedical Circuits and Systems conference

作者： Pinge, Sumukh Xu, Weihong Bittremieux, Wout Moshiri, Niema Jun, Sang-Woo Rosing, Tajana Univ Calif San Diego La Jolla CA 92093 USA Univ Antwerp B-2000 Antwerp Belgium Univ Calif Irvine Irvine CA 92697 USA

ISBN: (纸本)9798350354966;9798350354959

Mass spectrometry (MS) is essential for protein analysis but faces significant challenges with large datasets and complex post-translational modifications, resulting in difficulties in spectral identification. Open Modification Search (OMS) improves the analysis of these modifications. We present RapidOMS, a solution leveraging the Samsung SmartSSD, which integrates SSD and FPGA in a near-storage configuration to minimize data movement and enhance the efficiency of large-scale database searching. RapidOMS employs hyperdimensional computing (HDC), a brain-inspired, high-dimensional data processing approach, exploiting the parallel processing and low-latency capabilities of fpgas, making it well-suited for MS. Utilizing the parallelism and efficiency of bitwise operations in HDC, RapidOMS delivers up to a 60x speedup over the state-of-the-art (SOTA) CPU tool ANN-Solo and is 2.72x faster than the GPU tool HyperOMS. Furthermore, RapidOMS achieves an 11x improvement in energy efficiency compared to conventional systems, providing scalable, energy-efficient solutions for large-scale proteomics applications and advancing the efficient processing of proteomic data.

关键词： Mass Spectrometry Proteomics Hyperdimensional computing MS Library Searching fpgas

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reconfigurable PM2.5 Sensor Green Deployment Mechanism Based on Blockchain technology 1st

Reconfigurable PM2.5 Sensor Green Deployment Mechanism Based...

引用

1st International conference on Security and Information Technologies with AI, Internet computing, and Big data applications (SITAIBA)

作者： Chen, Hsing-Chung Liang, Yao-Hsien Hsu, Pei-Yu Asia Univ Dept Comp Sci & Informat Engn Taichung 413 Taiwan China Med Univ China Med Univ Hosp Dept Med Res Taichung 404 Taiwan

ISBN: (纸本)9783031054914;9783031054907

This paper presents the design of reconfigurable green PM2.5 sensor module deployment scheme based on blockchain technology. The proposed scheme proposes classes with hierarchical layers implemented by name registry smart contract that could be reconfigured for solving the green deployment problem among PM2.5 sensor modules. This proposed scheme design three functions made by smart contracts including Registration smart contract, Hierarchical Class Mapping Based on Name Registry Smart Contract Function, and reconfigurable Working Grouping Smart Contract Function. The results shown that the modules which are measured the similar data will be distributed into the candidate group instead of the current working group, where the total corresponding energy consumption will be reduced for the BC transaction operations in this blockchain network. Moreover, the relevant data storages will be also avoided to store the duplication data as well as redundant data.

关键词： reconfigurable green deployment Smart contract Name registry PM2.5 sensor module

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Enhancing Performance of Sigmoid Implementation in FPGA using Approximate computing

Enhancing Performance of Sigmoid Implementation in FPGA usin...

引用

2024 International conference on Informatics Electrical and Electronics, ICIEE 2024

作者： Murmu, Rohan Bhattacharya, Mahua Kumar, Somesh ABV-Indian Institute of Information Technology and Management Department of Information Technology M.P. Gwalior India ABV-Indian Institute of Information Technology and Management Department of Information Technology India ABV-Indian Institute of Information Technology and Management Department of Electrical and Electronics Engineering India

ISBN: (纸本)9798331519216

This paper explores an efficient implementation of the sigmoid function on Field-Programmable Gate Arrays (fpgas) through Piecewise Linear Approximation (PLAN). Recognizing the high computational demands of exact sigmoid calculations, we propose a methodology that leverages Approximate computing techniques to enhance performance. By strategically reducing precision, our approach significantly speeds up computations while maintaining acceptable accuracy levels, thus optimizing resource usage. This tradeoff is particularly advantageous in scenarios demanding high-speed data processing and low power consumption. We demonstrate the feasibility and benefits of our method with empirical results, suggesting its practicality for real-time applications in neural networks and machine learning. © 2024 IEEE.

关键词： Piecewise linear techniques

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Rayleigh Fading Modeling for reconfigurable Intelligent Surfaces under Different Number of Elements

Rayleigh Fading Modeling for Reconfigurable Intelligent Surf...

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2024 International conference on Decision Aid Sciences and applications, DASA 2024

作者： Mone, Bintang Vieshe Nuha, Hilal H. Putra Sailellah, Hassan Rizky Basri, Ailal Hamdi School of Computing Telkom University Bandung Indonesia School of Computing Telkom Indonesia Bandung Indonesia

ISBN: (纸本)9798350369106

This paper investigates the modeling of Rayleigh fading for reconfigurable Intelligent Surfaces (RIS) under varying numbers of surface elements. RIS, composed of two-dimensional grids with adjustable electromagnetic properties, has emerged as a promising technology for optimizing wireless communication. Rayleigh fading, a statistical model for signal fluctuations due to multipath propagation, is utilized to evaluate the performance of RIS-assisted communication. Through experimental analyses, including eigenvalue distributions and Signal-to-Noise Ratio (SNR) evaluations, the study highlights the spatial correlation properties and challenges of RIS, such as modeling accuracy and optimization strategies. Results indicate that RIS design and deployment significantly affect channel performance, providing insights for future wireless systems, particularly in 6G and beyond. © 2024 IEEE.

关键词： Signal to noise ratio

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