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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

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ShEF: Shielded Enclaves for Cloud fpgas 27

ShEF: Shielded Enclaves for Cloud FPGAs

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27th ACM International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zhao, Mark Gao, Mingyu Kozyrakis, Christos Stanford Univ Stanford CA 94305 USA Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450392051

fpgas are now used in public clouds to accelerate a wide range of applications, including many that operate on sensitive data such as financial and medical records. We present ShEF, a trusted execution environment (TEE) for cloud-based reconfigurable accelerators. ShEF is independent from CPU-based TEEs and allows secure execution under a threat model where the adversary can control all software running on the CPU connected to the FPGA, has physical access to the FPGA, and can compromise the FPGA interface logic of the cloud provider. ShEF provides a secure boot and remote attestation process that relies solely on existing FPGA mechanisms for root of trust. It also includes a Shield component that provides secure access to data while the accelerator is in use. The Shield is highly customizable and extensible, allowing users to craft a bespoke security solution that fits their accelerator's memory access patterns, bandwidth, and security requirements at minimum performance and area overheads. We describe a prototype implementation of ShEF for existing cloud fpgas, map ShEF to a performant and secure storage application, and measure the performance benefits of customizable security using five additional accelerators.

关键词： trusted execution enclaves cloud computing fpgas reconfigurable computing

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ILP Based Mapping for Elastic CGRAs 29

ILP Based Mapping for Elastic CGRAs

引用

29th IEEE International conference on Embedded and Real-Time computing Systems and applications, RTCSA 2023

作者： Saito, Makoto Kojima, Takuya Takase, Hideki Nakamura, Hiroshi Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan

ISBN: (纸本)9798350337860

In recent years, the emergence of deep learning and the need for big data analysis have created a demand for computers with high computational performance and energy efficiency. Since conventional ASICs and general-purpose CPUs cannot meet this requirement, domain-specific architectures that constrain applications are currently the focus of attention. Coarse-Grained reconfigurable Architecture (CGRA), one of the domain-specific architectures, is attracting attention because it is superior to CPUs and fpgas in terms of computational performance and power efficiency [1]. As depicted in Fig. 1, CGRA comprises a two-dimensional array of Processing Elements (PEs) and provides flexibility to change the instructions executed on the PEs and the connections between them, depending on the software being executed. On the other hand, the mapping problem for CGRA is an NP-complete problem, and there exist tradeoffs between solution accuracy and execution time. For real time applications, it is indispensable to shorten the mapping time. Thus, in this study, we propose an Integer Linear Programming (ILP) based mapping method for Elastic CGRA that aims to shorten mapping time while preserving solution accuracy. We have also implemented and preliminary evaluated the proposed method. © 2023 IEEE.

关键词： Mapping

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Cloud and Sensor-based Automation using Field Programmable Gate Array (FPGA) 14

Cloud and Sensor-based Automation using Field Programmable G...

引用

14th International conference on Advances in computing, Control, and Telecommunication Technologies, ACT 2023

作者： Chauhan, Aditya Patil, Shreyas S. Agrawal, Anita Jain, Aakash Chugh, Rishabh M. Reddy, K.S. Praneeth Department of Electrical and Electronics Engineering Birla Institute of Technology and Science-Pilani K.K Birla Goa Campus NH-17B Goa Zuarinagar403726 India

Cloud automation is one of the most promising and upcoming applications of IoT [1], as it allows users to control and monitor their environment remotely. Adopting the Internet of Things (IoT) in the automation industry has created an amazing opportunity to develop intelligent, automated systems. These systems can improve users' energy efficiency, security, and convenience. However, most automation systems based on microcontrollers may not be able to handle the complex and various tasks required in a modern environment. Field Programmable Gate Arrays (fpgas) replace microcontrollers, providing a more powerful, flexible, and scalable solution for the latest automation systems [2]. fpgas can perform multiple functions simultaneously, making them ideal for managing large amounts of sensor data and controlling signals in real-time. Moreover, fpgas are reconfigurable, enabling custom application creation and new features catering to the user’s specific needs. The ecosystem can also include voice assistants and AI-powered systems to learn user preferences and automate tasks. To create an effective ecosystem, devices must be compatible and communicate through a standard protocol like Bluetooth, Zigbee, Z-Wave, or Wi-Fi [13]. The ecosystem should also protect user privacy. A well-designed ecosystem can simplify daily tasks, increase comfort and convenience, and provide peace of mind by allowing users to monitor and control their systems remotely. © Grenze Scientific Society, 2023.

关键词： Internet of things

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Task Mapping for Hardware-Accelerated Robotics applications using ReconROS 6

Task Mapping for Hardware-Accelerated Robotics Applications ...

引用

6th IEEE International conference on Robotic computing, (IRC)

作者： Lienen, Christian Platzner, Marco Paderborn Univ Dept Comp Sci Paderborn Germany

ISBN: (纸本)9781665472609

Modern software architectures for robotics map tasks to heterogeneous computing platforms comprising multi-core CPUs, GPUs, and fpgas. fpgas promise huge potential for energy efficient and fast computation, but their use in robotics requires profound knowledge of hardware design and is thus challenging. ReconROS, a combination of the reconfigurable operating system ReconOS and the robot operating system (ROS) aims to overcome this challenge with a consistent programming model across the hardware/software boundary and support of event-driven programming. In this paper, we summarize different approaches for mapping tasks to computational resources in ReconROS. These approaches include static and dynamic mappings, and the exploitation of data parallelism for single ROS nodes. Further, for dynamic mapping we propose and analyse different replacement strategies for hardware nodes to minimize reconfiguration overhead. We evaluate the presented techniques and illustrate ReconROS' capabilites through an autonomous vehicle example in a hardware-in-the-loop simulation.

关键词： Robotics FPGA ROS 2 ReconROS

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A reconfigurable Approximate computing RISC-V Platform for Fault-Tolerant applications 27

A Reconfigurable Approximate Computing RISC-V Platform for F...

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27th Euromicro conference on Digital System Design

作者： Delavari, A. Ghoreishy, F. Shahhoseini, H. S. Mirzakuchaki, S. Iran Univ Sci & Technol Sch Elect Engn Tehran Iran

ISBN: (纸本)9798350380392;9798350380385

The demand for energy-efficient and high-performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named "phoeniX", using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy. The platform enables the integration of approximate circuits at the core level with diverse structures, accuracies, and timings without requiring modifications to the core, particularly in the control logic. The platform introduces novel control features, allowing configurable trade-offs between accuracy and energy consumption based on specific application requirements. To evaluate the effectiveness of the platform, experiments were conducted on a set of applications, such as image processing and Dhrystone benchmark. The core with its original execution engine, occupies 0.024mm(2) of area, with average power consumption of 4.23mW at 1.1V operating voltage, average energy-efficiency of 7.85pJ per operation at 620MHz frequency in 45nm CMOS technology. The configurable platform with a highly optimized 3-stage pipelined RV32I(E)M architecture, possesses a DMIPS/MHz of 1.89, and a CPI of 1.13, showcasing remarkable capabilities for an embedded processor.

关键词： Approximate computing Low Power Design RISC-V Embedded Processor Energy-Efficient Computation Very Large Scale Integration

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PAKSUPERCOMPUTER: AN OPEN-SOURCE, SCALABLE, AND HETEROGENEOUS SUPERcomputing PLATFORM

PAKSUPERCOMPUTER: AN OPEN-SOURCE, SCALABLE, AND HETEROGENEOU...

引用

2025 International conference on Energy, Power, Environment, Control and computing, ICEPECC 2025

作者： Hussain, Tassadaq Haider, Amna Centre for AI and Big Data Namal University Mianwali Mianwali Pakistan Pakistan Supercomputing Barcelona Supercomputing Center Spain

ISBN: (纸本)9781837243235

The recent advances in large vision and language models, along with generative artificial intelligence, have led to a growing demand for compute resources such as increased processing capacity, faster memory, and larger storage. In the current scenario, supercomputing is the only domain capable of solving complex and compute-intensive algorithms for large datasets. Thus, supercomputers are considered the backbone of all fields of academia, research, innovation, and commercialization. In this work, we propose and develop a Scalable Heterogeneous Supercomputer called PakSupercomputer. The PakSupercomputer uses heterogeneous processing cores, including multiple CPUs, Tensor Processing Units (TPUs), and Field Programmable Gate Arrays (fpgas). An Elastic Parallel Programming framework is deployed to provide an easy-to-use programming environment. This programming environment assists high-performance computing developers in writing applications without dealing with the complexities of heterogeneous distributed hardware architectures. The results confirm that when testing benchmarks with larger-scale, complex problems and cloud computing applications, the PakSupercomputer proves to be a low-power, Quadrillion Floating-Point Operations Per Second (FLOPS) supercomputer. © The Institution of Engineering & technology 2025.

关键词： Cluster computing

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Comparative Analysis and Enhancement of FPGA and ASIC Performance in Targeted applications 2nd

Comparative Analysis and Enhancement of FPGA and ASIC Perfor...

引用

2nd International conference on Artificial Intelligence and Communication Technologies, ICAICT 2024

作者： Lou, Haozhe School of Integrated Circuits Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9789819600953

Within the disciplines of electronic engineering and computer science, the quest for cutting-edge integrated circuit design has become more acute, reflecting the burgeoning need for high-performance computing solutions. This investigation delves into the comparative analysis of field-programmable gate arrays (fpgas) and application-specific integrated circuits (ASICs), scrutinizing their performance across a spectrum of application environments. The core of this study lies in discerning the contrasts between the two technologies in terms of design adaptability, operational velocity, energy conservation, and economic viability, alongside their consequent ramifications on practical applications. A hybrid research methodology is adopted, weaving together theoretical exposition with empirical investigations, including the application of performance evaluation models and the examination of real-world industrial case studies. Findings from the study reveal that fpgas boast superior adaptability in design and lower costs in the initial phase of development. Such attributes render them particularly advantageous for scenarios that necessitate swift product evolution and are limited to small-scale manufacturing. Conversely, ASICs exhibit enhanced capabilities in executing intricate tasks, most notably in the realms of large-scale data computation and sophisticated graphics processing. Moreover, the paper ventures into strategies for amplifying the energy efficiency of fpgas, considering advancements in development tools and microarchitectural refinements. The conclusive insights of the research articulate that fpgas and ASICs each possess distinct operational domains and strengths. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Application specific integrated circuits

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Advancing Digital Design: Integration of 16-Bit Unsigned Divider Capability in Xilinx's Kintex and Virtex FPGA Chips for Enhanced Computational Efficiency 13

Advancing Digital Design: Integration of 16-Bit Unsigned Div...

引用

13th IEEE International conference on Communication Systems and Network Technologies, CSNT 2024

作者： Shishir, Shrivastava Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798350305463

The addition of a 16-bit unsigned divider to Xilinx's Kintex and Virtex FPGA devices improves digital design and computational performance. Developers may divide nonnegative 16-bit integers with the 16-bit unsigned divider for precision numerical operations. Due to their hardware versatility and efficiency, fpgas may speed complicated algorithms in numerous application industries. Recognizable logic gates and programmable interconnects make fpgas versatile for digital signal processing, telecommunications, and fast prototyping. Xilinx's Kintex and Virtex series, known for customized designs and outstanding performance, get a 16-bit unsigned divider capability. Engineers may execute complex algorithms faster and more precisely with this innovation, opening up new possibilities in embedded systems, telecommunications, and more. Using HDLs like Verilog and VHDL makes FPGA programming easy, like software. When efficiency and speed are crucial, fpgas are essential in highperformance computing and real-time processing. Xilinx's Kintex and Virtex FPGA processors' 16-bit unsigned divider integration marks a major FPGA technical milestone. It simplifies calculation and widens digital designs, enabling designers to reach new possibilities. In this development, Xilinx's dedication to cutting-edge solutions shows how fpgas are becoming essential tools for a wide range of applications. Xilinx, FPGA, 16-bit unsigned division, computational efficiency, digital design, hardware acceleration, and highperformance computing are keywords for this work. © 2024 IEEE.

关键词： Field programmable gate arrays (FPGA)

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reconfigurable Compute in Memory Using SRAM and Bit Serial Algorithm 5

Reconfigurable Compute in Memory Using SRAM and Bit Serial A...

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5th International conference on Inventive Research in computing applications, ICIRCA 2023

作者： Deepa, A. Nirmalkumar, P. Jose, Deepa Tejendra Prasad, M.V. Anna University Ceg Campus Department of Electronics and Communication Engineering Chennai India Kcg College of Technology Department of Electronics and Communication Engineering Chennai India

ISBN: (纸本)9798350321425

In the past conventional von Neumann computer architecture, the data that are stored in the memory unit and the computing core are separated which leads to the increase in power consumption and latency as data size being increased In-memory computing, or compute in memory, aims to perform computer computations entirely within computer memory to eliminate these bottlenecks. One area of exploration for in-memory computing is deep neural network (DNN) acceleration through processing-in-memory platforms (PIM). Using bitwise digital multiplication, the digital CIM macro is designed with reconfigurable 1-8-bit input/weight and single sign bit. A column of bit cells makes up a column MAC, which performs a multiplication and accumulation operation, while dot product is computed by using a row of MACs functions as a single neuron. The bit cell includes three primary components: a user-defined 6T SRAM cell to store weight, for computing bitwise multiplication an XNOR gate is being used, and a carry look adder to accumulate partial sums. A digital CIM memory is designed using 64 × 64 SRAM bit cells for digital bit-serial computing was designed in 45-nm technology with 1-8-bit reconfigurable weight/input bits. © 2023 IEEE.

关键词： Deep neural networks

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Proceedings of the 13th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2023

Proceedings of the 13th International Symposium on Highly Ef...

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13th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2023

ISBN: (纸本)9798400700439

The proceedings contain 15 papers. The topics discussed include: extensible embedded hardware description languages with compilation, simulation and verification;breaking boundaries: optimizing FPGA CAD with flexible and multi-threaded re-clustering;efficient FPGA implementation of amoeba-inspired SAT solver with feedback and bounceback control: harnessing variable-level parallelism for large-scale problem solving in edge computing;quantitative study of floating-point precision on modern fpgas;resource-efficient RISC-V vector extension architecture for FPGA-based accelerators;CSA based Radix-4 Gemmini systolic array for machine learning applications;and noise resilience of reduced precision neural networks.

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