检索结果-内蒙古大学图书馆

8th International conference on computing in Engineering and technology, ICCET 2023

作者： Maurya, Omnik Kumar, Sandeep Department of ECE National Institute of Technology Delhi Delhi India

ISBN: (纸本)9781839539237

Now a day due to personal mobile and data networking like 4G and 5G systems, theamount of data that is being generated and uploaded over the cloud-based system isenormous. To perform AI on this data requires highly sophisticated data centers. Butsince modern processors are not tailor-made for AI based applications carrying out AIon them is very expensive. To cope up with this issue, research efforts are targetedover hardware-based acceleration methodologies like the use of GPUs, use of fpgasand custom-built ASICs to reduce the computational time. fpgas based hardwareaccelerators have gained lots of momentum because of faster development time andreconfigurability. This paper describes fpgas as a hardware accelerator (so calledInference Engine) to get inference for a software based trained Neural Network (NN).The maximum accuracy we get is of 94.02% for fully connected neural network forMNIST dataset. We demonstrate the accuracy for various activation functions withdifferent widths (8 bits, 16 bits and 32 bits). We also compare the resource utilization ofHigh-end FPGA and conclude on why a single FPGA board cannot be used to infer on large NN models. Finally, we also compare the throughput for such implementationand reason out why fpgas are popular for inferencing. © The Institution of Engineering & technology 2023.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design 32

FlexRoute: A Fast, Flexible and Priority-Aware Packet-Proces...

引用

32nd Euromicro International conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Zyla, Klajd Liess, Marco Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (纸本)9798350363074;9798350363081

As the world becomes more connected and new digital services emerge at a fast pace, the amount of network traffic increases rapidly. Consequently, processing requirements become more varied and drive the need for flexible packet-processing designs, especially as in-network computing gains traction. Traditional approaches deploy hardware accelerators in a pipeline in the sequence that the associated tasks are supposed to be executed. Hence, they do not accommodate flows with different processing requirements and provide no possibility to remap flows to task sequences in runtime. In order to address these limitations, we propose FlexRoute, a fast, flexible and priority-aware packet-processing design that can process network traffic at a rate of over 100 Gbit/s on fpgas. Our design consists of a reconfigurable parser and several processing engines that are arranged in a pipeline. The processing engines are equipped with processing units that execute specific tasks, flexible forwarding logic and priority-aware queuing/scheduling logic. We implement a prototype of FlexRoute in Verilog and evaluate it via cycle-accurate register-transfer level simulations. We also synthesize and implement our design on the Alveo U55C High Performance Compute Card and show its resource usage. The evaluation results demonstrate that FlexRoute can process packets of arbitrary size with different processing requirements at a traffic rate of about 70 Gbit/s significantly faster than two state-of-the-art flexible packet-processing designs.

关键词： In-network computing Packet processing Flexibility Scheduling SDN

来源：评论

学校读者我要写书评

暂无评论

Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on fpgas 34

Leveraging HBM2 for Accelerating k-mer Counting with oneAPI ...

引用

34th International conference on Field-Programmable Logic and applications (FPL)

作者： Lucas, Owen P. George, Alan D. Univ Pittsburgh NSF SHREC Ctr ECE Pittsburgh PA 15260 USA

ISBN: (纸本)9798331530082;9798331530075

Counting substrings of an arbitrary length k (k-mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data (>100s of GBs per genome), which need to be processed using frequent memory accesses into data structures considerably larger than available cache, leading to a memory-bound runtime. Stemming from the gap between processor and memory speed, this bottleneck requires alternative architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ highcapacity, high-bandwidth memory to address memory-bound tasks. This research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. The architecture was designed using Intel's oneAPI, which enables high-level synthesis for FPGA programming. The accelerator architecture was able to leverage inherent parallelism in the algorithm via the multiple parallel hash functions, along with partitioning data structure across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. The accelerator achieved 42.67M k-mers per second, 2.80x more than the throughput-optimized CPU version and 4.31x more than the original CPU app. Despite this speedup, the architectures saw diminishing returns when attempting to incorporate additional HBM2 banks. OneAPI was able to achieve speedup over the CPU using the FPGA and emerging memory, but it's somewhat limited in its current scaling capabilities.

关键词： Field programmable gate arrays bioinformatics high level synthesis hardware acceleration design tools memory management reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

Acceleration of Fully Connected Layers on FPGA using the Strassen Matrix Multiplication 5

Acceleration of Fully Connected Layers on FPGA using the Str...

引用

5th IEEE International conference on BioInspired Processing, BIP 2023

作者： Leon-Vega, Luis G. Chaon-Rodriguez, Alex Salazar-Villalobos, Eduardo Castro-Godinez, Jorge Università Degli Studi di Trieste Italy Instituto Tecnologico de Costa Rica Costa Rica

ISBN: (纸本)9798350330052

Deep Learning is one of the most popular techniques of Machine Learning (ML) but also one of the most computationally intensive and energy-demanding task in High-Performance computing (HPC), resulting in concerns about the sustainability of executing Artificial Intelligence massively. The challenge becomes harder when performing inference tasks at the Edge, where computational resources and energy are scarce. Field Programmable Gate Arrays (fpgas) are hardware-level reconfigurable devices with greater benefits in computer power vs energy consumption compared to CPUs and GPUs in the wide spectrum of HPC. High-Level Synthesis has helped reduce the complexity of using fpgas to accelerate algorithms using high-level languages like C++. This opens opportunities to research new hardware architectures for accelerating Deep Learning Inference (DLI) using fpgas for energy-constraint applications. Most ML applications involve Deep Neural Networks (DNNs), where matrix multiplication is one of the most popular operations. This work covers the optimisation of matrix multiplication by proposing a generic, HLS-compliant Strassen Matrix Multiplication Processing Element (PE) capable of adapting its implementation under different numerical precisions and hardware approximations. We discuss the PE's numerical and resource consumption analysis under several configurations and describe how it behaves in an actual DNN model dedicated to anomaly detection, spotting promising results for FPGA-based DLI at the Edge, saving up to 12.5% of DSP cells compared to the standard multiplication units on an XC7A50T (low-end FPGA) with negligible accuracy loss. © 2023 IEEE.

关键词： deep learning edge computing field programmable gate arrays high-level synthesis low-power electronics Strassen multiplication

来源：评论

学校读者我要写书评

暂无评论

The Future of Radar technology - Integrating RFSoC with reconfigurable computing for reconfigurable Radar Systems 4

The Future of Radar Technology - Integrating RFSoC with Reco...

引用

4th IEEE International conference on Electronic technology, Communication and Information, ICETCI 2024

作者： Chu, Oxygen Tiger Microwave Chengdu Chengdu China

ISBN: (纸本)9798350361643

In modern warfare and civilian applications, the rapid adaptability and high configurability of radar systems have become an urgent requirement. The limitations of traditional radar systems, particularly in terms of processing capabilities, adaptability, and power efficiency, call for a new solution. To address this, this paper proposes a radar system design that combines Radio Frequency System-on-Chip (RFSoC) technology with reconfigurable computing. This design aims to provide performance and functionality surpassing traditional radar architectures through integrated high-performance hardware and flexible software configurations. Leveraging the high integration capabilities of RFSoC, our design achieves seamless connectivity from the analog front-end to the digital back-end, allowing high-speed data acquisition, real-time signal processing, and multi-channel data synchronization to be accomplished on a single chip, significantly enhancing the overall efficiency of the system. This study elaborates on the hardware architecture design and software architecture design of the radar system, introducing the RFSoC-based multi-channel synchronization mechanism and wideband calibration technology. We employ a precise clock synchronization network and complex algorithms to ensure signal synchronization and consistency across the entire spectrum, enabling the system to support wideband operations and provide high-resolution radar imaging. By implementing a digital beamforming (DBF) algorithm based on fast Fourier transform (FFT), the system can process target signals from multiple directions and offers a software-defined approach to quickly adapt to new operational modes and task requirements. Experimental results demonstrate that the radar system not only achieves high-precision multi-beam transmission and reception in the 11 to 12 GHz frequency band but also exhibits outstanding performance in multi-target tracking and wideband signal processing. The profound significance

关键词： Beamforming

来源：评论

学校读者我要写书评

暂无评论

Analytical Performance Estimation for Large-Scale reconfigurable Dataflow Platforms

引用

ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2021年第3期14卷 1–21页

作者： Yasudo, Ryota Coutinho, Jose G. F. Varbanescu, Ana-Lucia Luk, Wayne Amano, Hideharu Becker, Tobias Guo, Ce Hiroshima Univ 1-4-1 Kagamiyama Higashihiroshima Hiroshima 7398527 Japan Imperial Coll London 180 Queens Gate London SW7 2BZ England Univ Amsterdam Postbus 94323 NL-1090 GH Amsterdam Netherlands Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa 2238522 Japan Maxeler Technol Ltd 3 Hammersmith Grove London W6 0ND England

Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today's technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as fpgas, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for reconfigurable Kernels and Systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

关键词： Performance modelling heterogeneous systems reconfigurable dataflow platforms fpgas

来源：评论

学校读者我要写书评

暂无评论

HardwareSupport for FPGA Resource Elasticity

HardwareSupport for FPGA Resource Elasticity

引用

作者： Aliyeva, Fidan KTH Royal Institute of Technology

学位级别：硕士

fpgas are commonly used in cloud computing due to their ability to be programmed as a processor that serves a specific purpose; hence, achieving high performance at low power. On the other hand, fpgas have a lot of resources available, which are wasted if they host a single application or serve a single user's request. Partially Reconfiguration technology enables fpgas to divide their resources into different regions and then dynamically reprogram those regions with various applications during runtime. Therefore, they are considered as a good solution to eliminate the underutilization resource problem. Nevertheless, the sizes of these regions are static; they cannot be increased or decreased once they are defined. Thereby, it leads to the underutilization of reconfigurable region resources. This thesis addresses this problem, i. e., how to dynamically increase/decrease partially reconfigurable FPGA resources matching an application's needs. Our solution enables expanding and contracting the FPGA resources allocated to an application by 1) application acceleration requirements expressed in multiple smaller modules which are configured into multiple reconfigurable regions assigned to the application dynamically and 2) providing a low - area - overhead, configurable, and isolated communication mechanism by adjusting crossbar interconnect and WISHBONE interface among those multiple reconfigurable regions.

关键词：

来源：评论

学校读者我要写书评

暂无评论

An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems 21

An Agile Tile-based Platform for Adaptive Heterogeneous Many...

引用

21st International conference on Field-Programmable technology (ICFPT)

作者： Kamaleldin, Ahmed Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

computing heterogeneity is a crucial demand for today's systems-on-chip requirements. Current many-core computing architectures feature a scalable number of heterogeneous compute units supporting a wide range of application domains. However, supporting both heterogeneity and computing scalability brings significant design challenges related to on-chip communication between heterogeneous components and run-time management. This leads to growing design time, development cost, and lack of hardware modularity and re-usability. This PhD work aims to develop and design a modular and adaptive hardware platform for realizing different types and taxonomies of heterogeneous many-core systems targeting fpgas reusing the same hardware components. The proposed platform is based on a modular and scalable tile-based architecture supporting heterogeneous instruction set architectures (ISAs), seamless integration of custom hardware accelerators and several memory hierarchies. In this paper, the proposed tile-based platform, preliminary results, and evaluation are presented targeting fpgas. Finally, planned and future works are highlighted.

关键词： reconfigurable computing heterogeneous many-core architectures field programmable gate arrays (fpgas)

来源：评论

学校读者我要写书评

暂无评论

Design of Multiband Frequency reconfigurable Antenna for WLAN/WIMAX/C/X/KU Band Application

Design of Multiband Frequency Reconfigurable Antenna for WLA...

引用

2024 OPJU International technology conference on Smart computing for Innovation and Advancement in Industry 4.0, OTCON 2024

作者： Gour, Sonam Singh, Ghanshyam Jain, Nikita Kumar, Durgesh Poornima College of Engineering Department of Electronics Engineering Jaipur India

ISBN: (纸本)9798350373783

The multi-functional ability in antennas is demanding for communications because the same device it could be used for different applications. The multi-functionality can be achieved by reconfiguration in terms of polarization, operating frequency or radiation pattern. The paper discussed the multifunctionality design of the Microstrip Antenna used Split Ring Resonator orthogonal shape circuit for frequency bands at 3.3 GHz;5.0 GHz;5.8 GHz;6.6 GHz;9.9 GHz and 15.9 GHz for WLAN, WiMAX, C, X and KU band wireless applications. PIN diode is used for reconfigure the device. A compact SRR loaded antenna with 50-ohm microstrip feed line is implemented. The operating bandwidth 11.81/4.27/4.29/6.62/3.27/4.22/8.13 are observed under simulation mode whereas 10.87 / 9.55 / 9.01 / 6.12 / 4.26 / 2.36 / 9.32 is achieved at resonant frequencies 2.4/3.0/3.5/5.0/5.8/11.8/13.1 GHz for wireless communication applications. The represented result shows that the design structure can be used further for the wireless applications due to its reconfiguration. © 2024 IEEE.

关键词： Microstrip antennas

来源：评论

学校读者我要写书评

暂无评论

A CPW Fed Hexagonal Patch Frequency reconfigurable Antenna for Multiple applications 3

A CPW Fed Hexagonal Patch Frequency Reconfigurable Antenna f...

引用

3rd International conference on Advances in Electrical, computing, Communication and Sustainable Technologies, ICAECT 2023

作者： Suman, Prem Nath Mishra, Gajendra Kant Birla Institute of Technology Mesra Electronics and Communication Engineering Ranchi India

ISBN: (纸本)9781665494007

This manuscript incorporates a coplanar waveguide fed a simple low-profile antenna to achieve frequency reconfigurability. The proposed structure in the PIN diode is attached in between the hexagonal patch and the rectangular slot. The Proposed frequency reconfigurable antenna structure provided frequency variations as the PIN Diode is switched. The resonating frequencies are 5.61 GHz, 9.59 GHz as PIN Diode is on, 6.74 GHz, 11.20 GHz, and 14.83 GHz as the PIN diode is off, providing maximum gain up to 7.73 dBi. This multiple-frequency variation of the antenna enables the antenna to use for multiple applications. © 2023 IEEE.

关键词： Coplanar waveguides

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：