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检索条件"任意字段=Conference on Simulation-Driven Modeling and Optimization"

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Circuit driven delay optimization of EMODL carry lookahead adders

Circuit driven delay optimization of EMODL carry lookahead a...

引用

Asilomar conference on Signals, Systems & Computers

作者： J. Wang Z. Wang G.A. Jullien S.S. Bizzan W. Luo W.C. Miller VLSI Research Group University of Windsor Windsor ONT Canada

Delay minimization of carry look-ahead adders using the enhanced multiple output domino logic (EMODL), is investigated. Delay versus tree height, using an analytical transistor sizing technique, is analyzed, and the trade-off between the tree height and the number of stages is discussed. Four architectures for a 32-bit adder are compared at the layout level and experiments show that the number of stages is more critical for delay optimization. Mask level simulations predict an aggressive 2.1 ns critical path for the best architecture using a 1.2 micron CMOS technology. The simulation procedure is verified by fabrication.< >

关键词： Delay Adders CMOS technology Circuit simulation Logic circuits Logic design Very large scale integration Computational modeling Fabrication Boolean functions

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Proceedings of the 30th ACM/IEEE Design Automation conference

Proceedings of the 30th ACM/IEEE Design Automation Conferenc...

引用

30th ACM/IEEE Design Automation conference, DAC 1993

ISBN: (纸本)0897915771

This conference proceedings contains 133 papers from a conference on logic circuit design automation. Topics discussed include asynchronous circuit design, sequential circuit analysis and optimization, fast algorithms for layout analysis, new ideas in technology mapping, logic circuit test generation, timing estimation and verification, optimization of analog circuits, optimal tree construction, high level design implementation, technology mapping for field programmable gate arrays, design for testability, extending the applicability of Boolean decision diagrams, information modeling, field programmable gate array layout and partitioning, digital signal processor synthesis, simulation and analysis of digital circuits, large-scale layout compaction, testing of delay and bridging faults, retiming and timing analysis in sequential synthesis, fault simulation and diagnosis, placement and floorplanning, performance-driven routing, advances in logic synthesis, high speed interconnects analysis, electrical modeling and simulation, and VLSI circuit partitioning.

关键词： Logic circuits

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16th IFIP Working Group 7.3 International Symposium on Computer Performance modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and modeling of Computer Systems, 1993

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16th IFIP Working Group 7.3 International Symposium on Computer Performance modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and modeling of Computer Systems, 1993

ISBN: (纸本)9783540572978

The proceedings contain 26 papers. The special focus in this conference is on Computer Performance modeling, Measurement and Evaluation. The topics include: Parallel simulation;properties and analysis of queueing network models with finite capacities;performance analysis and optimization with the power-series algorithm;multiprocessor and distributed system design;response time distributions in queueing network models;fast simulation of rare events in queueing and reliability models;an inlxoduction to modeling dynamic behavior with time series analysis;issues in trace-driven simulation;maximum entropy analysis of queueing network models;performance modeling using DSPN express;relaxation for massively parallel discrete event simulation;an overview of tes processes and modeling methodology;performance engineering of client-server systems;queueing networks with finite capacities;performance instrumentation techniques for parallel systems;a survey of bottleneck analysis in closed networks of queues;software performance engineering;performance measurement using system monitors;providing quality of service packet switched networks;dependability and performability analysis;architectures and algorithms for digital multimedia on-demand servers;analysis and control of polling systems;modeling and analysis of transaction processing systems.

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Flow-driven graphical user interface for parametric and statistical design optimization

Flow-driven graphical user interface for parametric and stat...

引用

Custom Integrated Circuits conference (CICC)

作者： C. Guardiani J. Benkoski Central Research and Development/DAIS Italy Zone Industrielle de Rousset Central Research and Development/DAIS Italy

A graphical user interface concept for a parametric and statistical design optimization system based on the response surface modeling (RSM) methodology is presented. The interface implements a new approach based on the interaction of the user with a graphical representation of the RSM flow which makes the algorithm easy and transparent to inexperienced users while also enforcing the correct sequence of operations in a very natural way. The learning time associated with the RSM methodology, which is now the main stumbling block for the widespread use of statistical design, can be considerably reduced. The application of this approach to parametric optimization has been implemented and verified with a practical example, giving excellent results.

关键词： Graphical user interfaces Design optimization Circuit simulation Computational modeling Response surface methodology Pluto Analytical models Polynomials Constraint optimization Command languages

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Locally optimistic methods of concurrent simulation

Locally optimistic methods of concurrent simulation

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European Design Automation conference

作者： D. Arvind Computer Science Department Edinburgh University Edinburgh UK

A new model is presented for the simulation of large and complex systems by exploiting concurrency. Composite ELSA is a distributed asynchronous event-driven simulation model which combines the conservative and optimistic synchronization protocols, while preserving their respective advantages. This model assigns synchronization classes to processes or a hierarchy of processes, which are based on attributes of conservatism or degree of optimism. These attributes can be dynamically updated during the course of simulation, enabling processes to switch smoothly between synchronization classes. A locally optimistic synchronization protocol is introduced, and comparisons are made with two traditional protocols for parallel logic simulation on distributed memory MIMD machines.< >

关键词： optimization methods Computational modeling Protocols Computer simulation Concurrent computing Discrete event simulation Switches Synchronization Clocks Computer science

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Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology

Non-local modeling of impact ionization for optimal device/c...

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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified conference (S3S)

作者： S. Krishnan J.G. Fossum Department of Electrical Engineering University of Florida Gainesville FL USA

Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS.< >

关键词： Impact ionization Predictive models MOSFETs Semiconductor device modeling Ultra large scale integration Electric breakdown Latches Physics Circuit simulation Design optimization

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PCUBE: A performance driven placement algorithm for low power designs

PCUBE: A performance driven placement algorithm for low powe...

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European Design Automation conference

作者： H. Vaishnav M. Pedram Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA

PCUBE, a performance driven placement algorithm for minimizing power consumption, is described. The problem is formulated as a constrained programming problem and is solved in two phases: global optimization and slot assignment. The objective function used during either phase is the total weighted net length, where net weights are calculated as the expected switching activities of gates driving the nets. Constraints on total path delays are also accounted for. On average, PCUBE reduces power consumption due to interconnect by 7% at the expense of 8% increase in the total wire length and 2% increase in circuit delay.< >

关键词： Algorithm design and analysis Circuit simulation Energy consumption Clocks Computational modeling Memory management Capacitance Delay Wire Circuit synthesis

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An association of simulated annealing and electrical simulator SPICE-PAC for learning of analog neural networks

An association of simulated annealing and electrical simulat...

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European conference on Design Automation

作者： G. Berthiau F. Durbin J. Haussy P. Siarry C.E.A. Départment Electronique et Instrumentation Nucléaire CEN de SACLAY Gif-sur-Yvette France Service Electronique Centre U C.E.A. Bruyeres le Chatel France Laboratoire Electronique et Physique Appliquee Ecole Centrale de Paris Chatenay-Malabry France

Simulated annealing adapted to continuous variables is used to determine the synaptic coefficients of an analog multilayer neural network, approximating any continuous function of one or several variables. The open electrical simulator SPICE-PAC driven by simulated annealing produces a globally optimal set of synaptic weights, in a reasonable time and without requiring heavy and inaccurate gradient computations. The authors illustrate and improve the weights-tuning strategy through two simple examples.< >

关键词： Simulated annealing Neural networks Multi-layer neural network Circuit simulation Resistors Computational modeling Feedforward neural networks Instruments Circuit optimization Analog circuits

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A computational environment for dextrous workspace analysis

A computational environment for dextrous workspace analysis

引用

ASME 1992 Design Technical conferences, DETC 1992

作者： Wang, J.Y. Wu, J.K. Department of Mechanical Engineering Center for Simulation and Design Optimization of Mechanical Systems University of Iowa Iowa CityIA United States

ISBN: (纸本)9780791897720

This paper presents an interactive engineering environment for dextrous workspace analysis of manipulators. The environment contains a mechanical system modeling tool, an automatic differentiation package, and numerical solvers that map onedimensional and two-dimensional solution sets of nonlinear parametrized kinematic constraint equations. Row-rank deficiency of constraint sub-Jacobian matrices is used as a necessary condition for characterizing the boundaries of the workspaces and dextrous workspaces of manipulators. A cursor driven animation capability, developed in an interactive graphics environment allows the user to retrieve system configurations by dragging the cursor along solution branches. An animation of the assembled configuration along that solution branch is then displayed. Thus, a better understanding of the kinematic behavior of mechanical systems that limits their dexterity can be obtained. A construction backhoe mechanical system is used to demonstrate the capability of the method developed. © 1992 American Society of Mechanical Engineers (ASME). All rights reserved.

关键词： Animation

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Circuit optimization driven by worst-case distances

Circuit optimization driven by worst-case distances

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IEEE International conference on Computer-Aided Design

作者： K.J. Antreich H.E. Graeb Institute of Electronic Design Automation Technical University Munich Munich Germany

A novel method for circuit optimization in the face of manufacturing process variations is presented. It is based on the characterization of the feasible design space by worst-case points and related gradients. The expense for this characterization is linear with the number of circuit performances. A deterministic optimization procedure based on the so-called worst-case distances is introduced, combining nominal and tolerance design in a single design objective. The entire optimization process with regard to performance, yield, and robustness uses sensitivity analyses and requires a much smaller number of simulations than the Monte-Carlo-based approaches. Moreover, the proposed method takes into account the partitioning of the parameter space into deterministic and statistical parameters which is an inherent property of integrated circuit design.< >

关键词： Circuit optimization Circuit simulation Monte Carlo methods Computational modeling Manufacturing processes Robustness Integrated circuit synthesis Cost function optimization methods Electronic design automation and methodology

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