In image sensors with passive pixels the column capacitance is large compared to the capacitance of the pixel. The charge-to-voltage conversion occurs in the column amplifier relatively far from the pixel. This may re...
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ISBN:
(纸本)0819427411
In image sensors with passive pixels the column capacitance is large compared to the capacitance of the pixel. The charge-to-voltage conversion occurs in the column amplifier relatively far from the pixel. This may result in a high sensitivity to interference, especially in case other electronic circuitry is located on the same chip. Two types of CIF CMOS imagers are presented that use different read-out options to counter this effect. Both designs use differential read-out as DRAM's do. This means that the pixel is compared to a reference cell. The first type uses a reference cell on the same row;the second type utilizes a fully symmetrical way of read-out, similar to digital memories by having its reference on the same column. Furthermore, two other means of image quality improvement are applied. A boost circuit is used to generate a negative voltage for driving the selecting transistor to insure that it is completely switched on during pixel reset. By this, threshold differences between pixels do not affect the reset voltage. The second is a well thought-out column amplifier that calibrates its offset before reading the pixel information.
Linear solid-state detectors are nowadays a widespread media in industrial and medical X-ray imaging. The resolution reached with this systems has been largely improved in this past years, but is still too poor for so...
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ISBN:
(纸本)0819427411
Linear solid-state detectors are nowadays a widespread media in industrial and medical X-ray imaging. The resolution reached with this systems has been largely improved in this past years, but is still too poor for some high resolution applications. We first have carried out an optimization of the detector characteristics through a behavioral simulation using a Hardware Description Language (HDLA(TM)). Furthermore, our work concerned the resolution enhancement for this kind of detectors via signal processing. Our approach takes into account the modeled point spread function (PSF) of the system. This modeled PSF is obtained with a new edge technique. The knowledge about the system response is used in a restoration scheme in order to improve the response of the detector to the high frequencies in the digital image. The restoration problem is an ill posed problem and uses an inverse Wiener filtering. Another intrinsic limitation of solid-state detectors is the spatial sampling step. In order to overcome this problem, we also tested the feasibility of a finer sampling of the acquired image, by interlacing several slightly shifted acquisitions of the same test object. The restoration applied to this finer sampled signal results in a resolution enhancement that is theoretically impossible to reach with a single detector acquisition. Some experimental results obtained on a variable bar-space pattern phantom are presented. This kind of phantom allows for a precise evaluation of the Modulation Transfer Function (MTF) on the acquired and processed images. The contribution of the image processing to the resolution enhancement can thus be quantified.
Today's imaging systems utilize fast operation to increase their throughput. At high line rates the illumination required to collect a reasonable image becomes prohibitive. Time delay and integration (TDI) offers ...
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ISBN:
(纸本)0819427411
Today's imaging systems utilize fast operation to increase their throughput. At high line rates the illumination required to collect a reasonable image becomes prohibitive. Time delay and integration (TDI) offers greatly enhanced responsivity to allow faster operation in terms of line rates. This combination of sensitivity and speed is unmatched in other sensor architectures. The standard multi-stage source follower output amplifier usually involves a trade off between speed and sensitivity through sizing of the first FET. We present a high bandwidth (>250 MHz) and sensitivity (>5 mu V/e), scaleable architecture for readout of TDI sensors. A key component of this architecture is the minimization of output amplifier load and parasitic capacitance. The methodologies used in the design and modeling of the output structure will be presented. This basic model has been confirmed over a range of device dimensions. A 4096 element, multi-tap TDI image sensor incorporating this architecture has been fabricated using a standard CCD process. Discrete and in-camera measurements will be presented demonstrating operation at >100 kHz line rates and with >300 V/(mu J/cm(2)) peak responsivity. Methods of controlling and reducing the stray loading on the sensor output will also be discussed.
In this paper, we present experimental results from measurements on CMOS APS imager designed by CIMI-SUPAERO on two different technologies. In both cases, pixels with photoMos and photodiode structures have been desig...
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ISBN:
(纸本)0819427411
In this paper, we present experimental results from measurements on CMOS APS imager designed by CIMI-SUPAERO on two different technologies. In both cases, pixels with photoMos and photodiode structures have been designed. The first circuit has been developed using a standard CMOS DLP/DLM 1.2 mu m process from Austria Micro Systems. The detector array consists of 32x32 square pixels with 50 mu m pixel pitch;fill factor is 75 % for photodiode (PD) and 50 % for photoMos (PM). The circuit is also including row and column address decoders and the readout circuitry so as to perform on-chip correlated double-delta sampling to reduce column to column fixed pattern noise. Two other chips have been developed with a standard CMOS SLP/DLM process from MIETEC with 0.7 mu m design rules, which includes a 128x128 pixels array, with 21 mu m pixel pitch and analogue readout circuitry. Among 10 different arrays, no faulty one was observed for both circuits. In this paper, we compare both performances of 32x32 pixels and 128x128 pixels in terms of dark current, quantum efficiency, conversion gain, dynamic range, linearity and spatial uniformity.
A large format (31 x 23 mm(2) display) CID imager module capitalizes on CID large well capacity and radiation resistance to image dental x-rays. The module, which consists of the imager, conversion phosphor and ancill...
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ISBN:
(纸本)0819427411
A large format (31 x 23 mm(2) display) CID imager module capitalizes on CID large well capacity and radiation resistance to image dental x-rays. The module, which consists of the imager, conversion phosphor and ancillary electronics, is encapsulated in a 40 x 28 x 5 mm(3) robust package that is lightproof, moisture-proof and meets FDA and RFL/EMI standards. Data exposure and readout is simple. The imager normally exists in an active reset mode until X-ray application automatically places the imager into a charge integration mode. Readout begins immediately upon completion of the x-ray exposure or manual application of an external trigger source. The imager returns to the reset mode once the data read out is complete. Pixels are arranged in an SVGA compatible 800(H) x 600(V) format. Each pixel is square and 38.5 microns/side. The imager is coated using a proprietary phosphor deposition process that results in a limiting resolution of 9 LP/mm from an X-ray illumination source. Better than 2,000:1 dynamic range and shot-noise limited operation is achieved. Direct X-ray detection and attendant noise is minimized via the phosphor and epitaxial layer that lies beneath the pixel array. The imager/module architecture and electro-optical performance are described in detail here in.
Charge-Transfer-Efficiency (CTE) is a parameter that is associated with the optical performance and radiometric accuracy of a Charge-Coupled Device (CCD). While modern CCD's are typically quoted as having CTE>0...
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ISBN:
(纸本)0819427411
Charge-Transfer-Efficiency (CTE) is a parameter that is associated with the optical performance and radiometric accuracy of a Charge-Coupled Device (CCD). While modern CCD's are typically quoted as having CTE>0.99999, we show that a) this efficiency can be degraded by exposure to energetic protons and b) the measured efficiency, at least in the case of irradiated devices, is dependent on the size of the signal being transferred. A comparison of two techniques of CTE measurement is presented, with emphasis on an Fe-55 X-ray charge-generation and collection technique tailored especially for use with linear CCD's. While our technique follows the same general X-ray method widely used to characterize area CCD's, its implementation, including the processing of the resulting experimental data, is somewhat novel. The X-ray technique requires no special device circuitry or equipment and, in our configuration, may be used on virtually any linear or bilinear CCD;the same general technique is used on area arrays. It is shown that the technique is appropriate for characterizing small-signal CTE with or without a high background. It is also shown that the electrical injection CTE, while requiring the injection circuitry to be designed and built-in to the CCD structure, is more appropriate for large-signal CTE measurement. Data are presented showing experimental pre-and post-irradiation CTE measured as a function of signal level and background level for a two-phase linear CCD. Additionally, it is shown that in our tests, the CTE degraded even at very small accelerated doses (<10 kRad(Si) of ionizing proton dose), but further degradation was at least partly compensated by an enhanced background due to increasing dark currents.
Photodiode devices, in which the photosite consists of a reverse biased pn diode, have excellent quantum efficiencies at visible wavelengths and in the UV. However they display high levels of dark and bright image lag...
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ISBN:
(纸本)0819427411
Photodiode devices, in which the photosite consists of a reverse biased pn diode, have excellent quantum efficiencies at visible wavelengths and in the UV. However they display high levels of dark and bright image lag, and high levels of fixed pattern noise (FPN) when operated with electronic shuttering (exposure control). We have addressed these performance issues by replacing the photodiode photosites with pinned photodiode (PPD) photosites. In the PPD the n+ region of the conventional photodiode is replaced by a n region and a shallow highly doped p region - the surface potential in the photosite is pinned such that the photosite behaves as an ungated buried channel well. The high quantum efficiencies associated with photodiodes are maintained while allowing for large reductions in image lag and fixed pattern noise. We have developed PPD processes for two different photosite architectures. In the first architecture, charge is generated in the PPD and immediately spills to an adjacent gated integration well. In the second architecture, the charge is generated and stored in the PPD. Each of the architectures can be configured to allow for antiblooming/electronic shuttering. Both of the PPD processes and their associated architectures have been characterized, and order of magnitude reductions in image lag have been observed for PPD photosites relative to conventional photodiodes. No degradation in QE, PRNU, or well capacity has been observed. One of the PPD processes has been implemented in a family of high speed, quad output, linear sensors with 100 MHz data rates. Performance results are presented.
Shrinkage of pixel structures and layouts for CMOS Active Pixel Image sensors (APS's) are studied. Reduction of CMOS device design rule with the scaling-law can make the pixel size small, naturally. However, using...
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ISBN:
(纸本)0819427411
Shrinkage of pixel structures and layouts for CMOS Active Pixel Image sensors (APS's) are studied. Reduction of CMOS device design rule with the scaling-law can make the pixel size small, naturally. However, using minimum design rule, quarter micron rule or sub quarter micron rule, costs expensive. Therefore, pixel size shrinkage using relatively rough design rule have been studied for reduction of the chip cost. We have already reported about small pixel structure by replacement of row-select transistor by row-select capacitor, by omission of reset transistor with forward bias reset operation, and by omission of reset transistor with pinned-buried reset channel. We have also reported about small pixel by high packing density layout named "I-shaped cell" and its zigzag layout. However, these pixel shrinkage have some disadvantages. In this paper, we propose a novel pixel structure driven by pulse operation of drain line for row select and reset. Conventional row select structure, row select transistor or row select capacitor, is omitted by the row-select channel that contains low impurity concentration and has no gate structure. Moreover, conventional reset transistor is also replaced by reset channel structure in like manner. These structures and triple level pulse operation of drain realize quite simple pixel structure in which amplification transistor is the only gate structure. A large fill factor of 37% is obtained by this structure, in 5.6 mu m x 5.6 mu m pixel designed by 0.7 mu m rule.
development of light emitting diodes (LEDs) and arrays of diodes to be utilized in a modern and highly sensitive spectrophotometer is presented. The In1-xGaxAs1-yPy quaternary alloy semiconductor has been utilized in ...
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development of light emitting diodes (LEDs) and arrays of diodes to be utilized in a modern and highly sensitive spectrophotometer is presented. The In1-xGaxAs1-yPy quaternary alloy semiconductor has been utilized in the design and fabrication of surface emitting infrared LEDs in the spectral range from 1100 to 1650 nm. Custom made chips provide the surface-emitting LEDs with high radiance and superior far-field patterns. The hybrid 31-element array of LEDs was fabricated. A temperature sensor and a photodiode was incorporated on the hybrid circuit to control the temperature and light intensity of the diodes. The instrument prototype has been fabricated and preliminary experimental data have been collected. (C) 1998 Elsevier Science S.A. All rights reserved.
development of light emitting diodes (LEDs) and arrays of diodes to be utilized in a modern and highly sensitive spectrophotometer is presented. The In1-xGaxAs1-yPy quaternary alloy semiconductor has been utilized in ...
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development of light emitting diodes (LEDs) and arrays of diodes to be utilized in a modern and highly sensitive spectrophotometer is presented. The In1-xGaxAs1-yPy quaternary alloy semiconductor has been utilized in the design and fabrication of surface emitting infrared LEDs in the spectral range from 1100 to 1650 nm. Custom made chips provide the surface-emitting LEDs with high radiance and superior far-field patterns. The hybrid 31-element array of LEDs was fabricated. A temperature sensor and a photodiode was incorporated on the hybrid circuit to control the temperature and light intensity of the diodes. The instrument prototype has been fabricated and preliminary experimental data have been collected.
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