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检索条件"任意字段=Conference on VLSI Circuits and Systems V"

共 1520 条记录，以下是1-10 订阅

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Hybrid Dadda-Capprox Multiplier Architecture for Energy-Efficient High-Speed CNN Processing in vlsi

Hybrid Dadda-Capprox Multiplier Architecture for Energy-Effi...

引用

2025 IEEE International Students' conference on Electrical, Electronics and Computer Science, SCEECS 2025

作者： Asha, S. varalakshmi, S. Kalarani, G. Priya, S.v. Saveetha Engineering College Department of Ece Tamil Nadu Thandalam Chennai India Bharath Institute of Higher Education and Research Department of Ece Tamil Nadu Chennai India Jaya Engineering College Department of Eie Tamil Nadu Chennai India Loyola Institute of Technology Department of Ece Tamil Nadu Chennai India

ISBN: (纸本)9798331529833

A New Dadda-Capprox multiplier that combines Dadda and Capprox multipliers can improve the energy and speed performance for CNN applications on vlsi circuits. Conventional multiplier structures may not achieve an optimal power-performance methodology, where speed is critical in CNN implementations. To overcome this issue, the hybrid multiplier that has been proposed incorporates the fast Dadda tree structure and the power-saving Capprox multiplier while adjusting the precision that is lost to gain a massive amount of efficiency. The experimental result provides a better improvement of 45.7% in energy efficiency and a 54.7% less PDP when compared with the conventional multiplier. Also, the hybrid architecture achieves a high CNN classification accuracy of 92.3% while operating at 8 bits of approximation, achieving fast execution and low power consumption. These effectiveness results reinforce that the proposed architecture may be useful for real-time, energy-restricted devices, as CNN execution on vlsi systems that require high operation efficiency for implementing specific tasks by addressing crucial concerns such as low power usage, size, and relatively high clock frequencies. © 2025 IEEE.

关键词： vlsi circuits

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Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs 38

Optimization of Sub-Threshold Standard Cells for Energy Effi...

引用

38th International conference on vlsi Design, vlsiD 2025

作者： Suroshi, vardhan Karthik, B.K. Kannur, vikram Reddy, vinay Purnaprajna, Madhura PES University Centre for Heterogeneous and Intelligent Processing Systems India InCore Semiconductors India

ISBN: (纸本)9798331522445

Energy efficiency is a critical focus in contemporary integrated circuit (IC) design, particularly for ultra-low power applications. Subthreshold voltage scaling presents a promising solution for reducing energy consumption, though it introduces performance challenges that necessitate custom design libraries. This work presents a comprehensive methodology for creating a specialized subthreshold standard cell library, utilizing the SPEA-2 genetic algorithm for optimal transistor sizing.1 Our library demonstrates an average improvement in energy efficiency of 44% compared to conventional approaches. We validate its performance by synthesizing RISC-v processors and EPFL benchmark circuits, comparing them with standard foundry libraries operating at nominal (1.2 v) and near-threshold (600 mv) voltages. The results show a 13.26× and 1.49× reduction in energy consumption, respectively, for the subthreshold library. However, this comes with a 5.21× and 1.3× increase in area, respectively. These findings underscore the viability of subthreshold libraries as an effective option for energy-constrained designs. © 2025 IEEE.

关键词： Genetic algorithms

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A 0.75mm2407µW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices 38

A 0.75mm2407µW Real-Time Speech Audio Denoiser with Quantiz...

引用

38th International conference on vlsi Design, vlsiD 2025

作者： Kochar, Dimple vijay Ashok, Maitreyi Chandrakasan, Anantha P. Massachusetts Institute of Technology Electrical Engineering and Computer Science CambridgeMA United States

ISBN: (纸本)9798331522445

Audio denoising is crucial for delivering high-quality sound in applications ranging from communication devices to entertainment systems. On-device denoising is critical for en-suring consistent performance across various host platforms. Machine learning (ML) models exhibit strong audio processing performance in the frequency domain but require efficient hardware design. This paper focuses on enhancing audio quality using convolutional encoder-decoder ML models with low power consumption while meeting real-time processing constraints. We achieve this by developing a quantized network that optimally reduces computational costs without compromising enhancement quality. Furthermore, our hardware quantization scheme reduces memory usage by up to 75% while maintaining accuracy. Next, we design a complementary processing element activation routing scheme tailored to our algorithm, significantly reducing the on-chip memory accesses by 5-9×. Fabricated in 28nm CMOS process, our chip demonstrates real-time audio denoising, processing each frame within 8ms while consuming only 407µ or 3.24 µJ/frame at 0.65v, 18.5 MHz, making it ideal for battery-powered IoT devices. In terms of performance, our chip also achieves the highest evaluation score for audio quality (PESQ), outperforming previous works. © 2025 IEEE.

关键词： CMOS integrated circuits

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Design and Analysis of a Novel High-Performance Adder Circuit for vlsi Applications

Design and Analysis of a Novel High-Performance Adder Circui...

引用

International conference on systems, Control and Automation, ICSCA 2023

作者： Chaurasia, Himanshu Chandel, Rajeevan Scholar ECE Department NIT Hamirpur HP Hamirpur177005 India ECE Department NIT Hamirpur HP Hamirpur177005 India

ISBN: (纸本)9789819773831

In the present paper, a 1-bit hybrid full adder (HFA) is designed and presented. The HFA essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The proposed circuit has a performance upper edge in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and Power-delay-number of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior HFAs reported in the literature, the suggested circuit offers superior space demands and power. The proposed circuit is also analyzed with voltage scaling, and it is found that it offers the best performance at 1.2 v supply voltage. Compared to current one-bit hybrid full adder circuits, simulation findings demonstrate that the suggested design displays lower power consumption, lower PDP, requires fewer transistors, and lower PDNP value. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Transistors

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n-Bit ALU using CMOS Forced Transistor Stacking

n-Bit ALU using CMOS Forced Transistor Stacking

引用

Trends in Material Science and Inventive Materials (ICTMIM), International conference on

作者： Srividya B v Manasi v varma Nidhi Mukesh Ishwarya S Kavita S Electronics and Telecommunication Engineering Dayananda Sagar College of Engineering Bengaluru Karnataka India

ISBN: (数字)9798331501488

ISBN: (纸本)9798331501495

This paper proposes the design of an n-bit ALU using CMOS Forced Transistor Stacking, emphasising its performance based on power consumption and delay compared to CMOS circuits. While CMOS designs are widely used, they suffer from high power consumption and latency. In comparison, Forced Transistor Stacking boosts the effective resistance under idle conditions and reduced leakage power by connecting transistors in series. Each block of the suggested ALU design is made up of forced stack transistor circuits and is intended to carry out fundamental arithmetic and logical operations. Using Cadence virtuoso for simulation and evaluation, this paper highlights the advantages of stacked transistors based on parameters like delay, power consumed and transistor count. The potential of forced transistor stacking as a practical technique for upcoming low-power vlsi designs is highlighted in the study. It exhibits advantages in reduced power leakage, increased power efficiency, scalability for dense systems and thermal benefits. These features make this technique an attractive solution for modern, low-performance, and high-performance digital systems.

关键词： Resistance Power demand Scalability Stacking circuits Computer architecture CMOS technology Delays Power dissipation Transistors

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Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs

Optimization of Sub-Threshold Standard Cells for Energy Effi...

引用

International conference on vlsi Design

作者： vardhan Suroshi Karthik B K vikram Kannur vinay Reddy Madhura Purnaprajna Centre for Heterogeneous and Intelligent Processing Systems PES University India InCore Semiconductors India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Energy efficiency is a critical focus in contemporary integrated circuit (IC) design, particularly for ultra-low power applications. Subthreshold voltage scaling presents a promising solution for reducing energy consumption, though it introduces performance challenges that necessitate custom design libraries. This work presents a comprehensive methodology for creating a specialized subthreshold standard cell library, utilizing the SPEA-2 genetic algorithm for optimal transistor sizing. 1 Our library demonstrates an average improvement in energy efficiency of 44% compared to conventional approaches. We validate its performance by synthesizing RISC-v processors and EPFL benchmark circuits, comparing them with standard foundry libraries operating at nominal (1.2 v) and near-threshold (600 mv) voltages. The results show a 13.26× and 1.49× reduction in energy consumption, respectively, for the subthreshold library. However, this comes with a 5.21× and 1.3× increase in area, respectively. These findings underscore the viability of subthreshold libraries as an effective option for energy-constrained designs.

关键词： Energy consumption Program processors Memory management voltage very large scale integration Libraries Energy efficiency Transistors Standards Optimization

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design

Meta-Heuristic Optimization of Custom Heterogeneous Blocks D...

引用

International conference on vlsi Design

作者： D v Bhargav G Pradyumna Madhav Rao IIIT Bangalore

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modern Field-Programmable Gate Arrays (FPGAs) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, FPGAs are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). The proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable Logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. The results showed a significant improvement of 44.62% in hardware parameters.

关键词： Layout Metaheuristics Digital signal processors Signal processing algorithms Computer architecture Silicon Fabrics Logic IP networks Field programmable gate arrays

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Hybrid Dadda-Capprox Multiplier Architecture for Energy-Efficient High-Speed CNN Processing in vlsi

Hybrid Dadda-Capprox Multiplier Architecture for Energy-Effi...

引用

IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： S. Asha S. varalakshmi G. Kalarani S.v. Priya Department of ECE Saveetha Engineering College Thandalam Chennai Tamil Nadu India Department of ECE Bharath Institute of Higher Education and Research Chennai Tamil Nadu India Department of EIE Jaya Engineering College Chennai Tamil Nadu India Department of ECE Loyola Institute of Technology Chennai Tamil Nadu India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

关键词： Energy consumption Accuracy Power demand Computer architecture very large scale integration Real-time systems Energy efficiency Hybrid power systems Convolutional neural networks Testing

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An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural Network

An Experimental Demonstration of Neuronal Somatic Behavior U...

引用

International conference on vlsi Design

作者： Anshul Awasthi Soumi Saha Parikshit Sahatiya Surya Shankar Dan Department of Electrical & Electronics Engineering Birla Institute of Technology and Science (BITS) Pilani India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This report presents the fabrication and characterization of a 2D SnS memristor, proposing its integrate and fire (I&F) model as a potential hardware implementation of neuronal somatic behavior. The memristor comprises a thin layer of tin(II) sulfide (SnS) sandwiched between copper (Cu) electrodes on a silicon (Si) substrate. This structure exhibits an impressive $R_{off}:R_{on}$ ratio of 103 at a read voltage $v_{read}$ of 0.25 v with an exceptionally low switching voltage $v_{swit\mathrm{c}h}$ of 0.3 v, with $\sim 3$ order variation between the maximum $R_{\max}$ and minimum resistance $R_{\min}$ offered during single voltage sweep cycle. We have explained the memristive behavior using the dual ionic conduction mechanism in the SnS active layer. With the help of Ultraviolet Photoelectron Spectroscopy (UPS), we have extracted the real-time band diagram of SnS, that explains the ultra-low $v_{switch}$ . We propose that the emulation of the I&F artificial neuron model exhibited by the fabricated device could serve as a promising application in the field of artificial neuron spiking. Finally, an equivalent neuronal spike generator circuit has been designed and its response has been shown to emulate the experimentally demonstrated somatic behavior, that can be used for neuromorphic circuit designs.

关键词： Fabrication Neuromorphics Neurons Memristors voltage Switches Silicon Integrated circuit modeling Uninterruptible power systems Switching circuits

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Startup Circuit for Relaxation Oscillators with Low Functional Current and Minimal Area

Startup Circuit for Relaxation Oscillators with Low Function...

引用

International conference on vlsi Design

作者： Anubhav Srivastava Sadique Mohammad Iqbal Divya Tripathi Saurabh Goyal Mixed Signal IP NXP Semiconductors Pvt. Ltd Noida India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This paper presents a novel start up technique for low current, low area, closed loop relaxation oscillator. In the proposed implementation, start-up time is improved by keeping the circuit initially in open loop and then in closed loop when the frequency is settled. In open loop mode, current is injected in the ring oscillator to charge the internal nodes. This results in approximately 3x improvement in start-up time (from 466us to 150us) across process, voltage, and temperature variations. This is achieved without increasing the functional current of the oscillator which consumes 52 nanoamperes of current. The start-up circuit is implemented by using current mirrors and digital circuits which do not require large area and offer very less leakage current. Proposed circuit is implemented in 16FFC technology for a 32KHz, 94nW relaxation oscillator circuit. The circuit operates on 1.8v (+/−10%) supply voltage and over a temperature range of-40°C to 125°C. The oscillator circuit shows +/− 5% post trim frequency variation across voltage and temperature.

关键词： Ring oscillators Frequency locked loops Time-frequency analysis Temperature distribution Embedded systems Simulation voltage very large scale integration Leakage currents Oscillators

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