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Camera mote with a high-performance parallel processor for real-time frame-based video processing

Camera mote with a high-performance parallel processor for r...

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IEEE conference on Advanced Video and signal Based Surveillance (AVSS)

作者： Richard Kleihorst Anteneh Abbo Ben Schueler Alexander Danilin NXP Research and Philips Research Eindhoven Netherlands

This paper describes a new smart camera mote with a high performance SIMD (single-instruction multiple-data) processor. Previous versions of our camera mote were equipped with IC3D, a line-based processor. The mote described in this paper is equipped with Xetal-ii, a processor designed for frame-based real-time video analysis. The processor uses 320 processing elements in parallel to achieve performance figures of more than 100 GOPS with a power consumption of 600 mWatt at peak performance. The IC has a 10 Mbit internal memory cache to store and work on 4 VGA frames. The internal bandwidth to this memory is more than 1.5 Tbit/s allowing multiple passes over the images within frametime. Augmented with hardware tools for object processing, the new mote opens the door for embedded active vision applications and other iterative techniques such as watershedding and distance transforms in collaborative camera networks.

关键词： Smart cameras Layout Energy consumption Ambient intelligence Filters Computer architecture Application software Wireless sensor networks image processing Parallel processing

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Hyper Spectral image compression using Higher Order Orthogonal Iteration Tucker decomposition

Hyper Spectral Image compression using Higher Order Orthogon...

引用

IEEE India conference (INDICON)

作者： B. Sucharitha K. Anitha Sheela Electronics and Communication Engineering Jawaharlal Nehru Technological University Hyderabad India

ISBN: (纸本)9781665452724

Hyper spectral images need more memory to store, process, and transmit due to the large amount of information they carry. One of the most effective way to compress hyper spectral images is to represent them as a three-dimensional tensor. Tensors are multi-dimensional Structures. Tensors have a wide range of applications in numerical linear algebra, chemometrics, data mining, signal processing, statics, data mining, and machine learning. For dimensional reduction of tensors, many tensor decomposition methods have been developed, which we can adapt to Hyper spectral image compression. The proposed method uses Discrete wavelet Transform and Higher-Order Orthogonal Iteration Tucker Decomposition method to compress the Hyper spectral image. The simulation results were compared with 3 more tensor decomposition techniques. Four real hyper spectral images were used in the experimentation: Pavia University (610 X 340 X 103), Indian Pines adjusted (145 x 145 x 200), Salinas image (512 x 217 x 224), and Abu-beach (150 X 150 X 102). After processing, the perceptional quality of the Hyper spectral images is evaluated using PSNR and SSIM. When compared to the other three methods, the proposed method offers good PSNR and SSIM with High Compression.

关键词： Tensors image coding Three-dimensional displays Simulation Memory management Termination of employment Transforms

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Classification of left/right hand movement from EEG signal by intelligent algorithms

Classification of left/right hand movement from EEG signal b...

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International conference on Computer applications and Industrial Electronics (ICCAIE)

作者： Muhammad Zeeshan Baig Ehtasham Javed Yasar Ayaz Waseem Afzal Syed Omer Gillani Muhammad Naveed Mohsin Jamil Department of Robotics and Artificial Intelligence Robotics and Intelligent Systems Engineering (RISE) Lab Islamabad Pakistan Centre for Intelligent Signal and Imaging Research (CISIR) Universiti Teknologi PETRONAS Malaysia Department of Electronic Engineering Mohammad Ali Jinnah University Islamabad Pakistan

Brain Computer interface (BCI) shown enormous ability to advance the human way of life. Furthermore its application is also targeting the disabled ones. In this research, we have implemented a new approach to classify EEG signals more efficiently. The dataset used for this purpose is from BCI competition-ii 2003 named Graz database. Initial processing of the EEG signals has been carried out on 2 electrodes named C3 & C4; after that the bi-orthogonal wavelet coefficients, Welench Power Spectral Density estimates and the average power were used as a feature set for classification. We have given a relative study of currently used classification algorithms along with a new approach for classification i.e. Self-organizing maps (SOM) based neural network technique. It is used to classify the feature vector obtain from the EEG dataset, into their corresponding classes belong to left/right hand movements. Algorithms have been implemented on both unprocessed features and processed reduced feature sets. Principal component Analysis (PCA) has been used for feature reduction. Measured data revealed that the maximum classification accuracy of 84.17% on PCA implemented reduce feature set has been achieved using SOM based classifier. Furthermore, the classification accuracy has been increased about 2% by simply using bi-orthogonal wavelet transform rather than Daubechies wavelet transform.

关键词： Feature extraction Electroencephalography wavelet transforms Classification algorithms Support vector machine classification Electrodes

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Evaluation of the performance of block matching algorithms in wavelet-based t+2D video coding

Evaluation of the performance of block matching algorithms i...

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International conference on Microelectronics, ICM

作者： M. Marzougui A. Zoghlami M. Atri R. Tourki Faculty of Sciences at Monastir Laboratory of Electronic and Microelectronic University of Monastir Monastir Tunisia

Motion estimation is the process of determining the movement of blocks between adjacent video frames by which image information is assessed for similarities that can be reused in subsequent frames. However, computational complexity and resource sharing of the motion estimation algorithm poses great challenges for real time applications. Fast search algorithms emerged as important search technique to achieve real time tracking results. Among the different motion estimation algorithms block matching is the most common used technique. This paper presents a system-level implementation of a wavelet-based t+2D video coding. Three block matching motion estimation algorithms are implemented in order to evaluate the overall system performance. In fact, since the chip design and layout process is time consuming and expensive, it is very important to be able to predict the overall system performance in a highlevel implementation before its circuit layout is deployed. The aim is to discuss the impact of different block matching motion estimation algorithms on video coding performance. Because of the complexity of the entire motion estimation system, decision in choosing one algorithm versus the other algorithms is often empirical and crucial.

关键词： Motion estimation PSNR wavelet transforms signal processing algorithms Cost function Vectors

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An embedded scaling-based arbitrary shape region-of-interest coding method for JPEG2000

An embedded scaling-based arbitrary shape region-of-interest...

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International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： M.M. Subedar L.J. Karam G.P. Abousleman Department of Electrical Engineering Arizona State University Tempe AZ USA Compression Communications & Intelligence Laboratory General Dynamics Decision Systems Scottsdale AZ USA

The shape information of objects is perceptually very significant and can aid in the recognition of objects. Depending upon the bit budget, Internet browsing applications can take advantage of an arbitrary-shape region-of-interest (ROI) coding method by sending only the shape information first, and then progressively transmitting the ROI texture, followed by the less important non-ROI texture information. Unfortunately, the existing ROI coding methods, including the JPEG2000-based methods, do not support separate coding and decoding of the shape information. In particular, the maxshift and the scaling-based methods of JPEG2000 are limited in that the former does not allow the coding of any non-ROI bitplanes prior to the coding of the ROI bitplanes, and the latter supports only rectangular and circular ROIs. The paper presents a novel ROI-based coding method that extends the scaling-based method of JPEG2000, and allows the coding of arbitrary-shape ROIs, as well as the separate coding and transmission of the ROI shape information prior to the texture information. Coding results are presented to illustrate the performance of the proposed ROI-based coding method.

关键词： Shape Transform coding Decoding Discrete wavelet transforms Internet Biomedical imaging Object detection Pixel image coding Block codes

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Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000

Analysis and Architecture Design for Memory Efficient Parall...

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International conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Lien-Fei Chen Tai-Lun Huang Tzau-Min Chou Yeong-Kang Lai Department of Electrical Engineering National Chung Hsing University Taichung Taiwan

In this paper, a memory efficient parallel embedded block coding (EBC) architecture with throughput enhancement in JPEG 2000 applications is proposed. In order to reduce the memory size, the memory-free algorithm for state variables in the context formation (CF) is proposed. The proposed algorithm eliminates the state variable memories by calculating three coding state variables (gamma p+1 [n], sigma p+1 [n], and pi p [n]) on the fly. We also propose the stripe-column-based pass-parallel operation to perform three coding passes and four samples within the stripe-column concurrently. The FIFO architecture between the high throughput CF and the arithmetic encoder (AE) is also optimized by the pipelined sorter and the parallel-in parallel-out register file. Owing to the proposed high parallel CF, we propose a parallel and two-stage pipelined AE architecture to deal well with the context/decision (CX/D) pairs for three coding passes. The experimental results show that memory size of the proposed architecture is smaller than other familiar architectures, and the proposed architecture can process the lossless coding about 50 MSamples/sec at 100-MHz

关键词： Memory architecture Block codes Throughput Arithmetic Transform coding Discrete wavelet transforms Partitioning algorithms IEC standards ISO standards image coding

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BP-DIP: A Backprojection based Deep image Prior

BP-DIP: A Backprojection based Deep Image Prior

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European signal processing conference (EUSIPCO)

作者： Jenny Zukerman Tom Tirer Raja Giryes Tel Aviv University Tel Aviv Israel School of Electrical Engineering Tel Aviv University Tel Aviv Israel

ISBN: (数字)9789082797053

ISBN: (纸本)9781728150017

Deep neural networks are a very powerful tool for many computer vision tasks, including image restoration, exhibiting state-of-the-art results. However, the performance of deep learning methods tends to drop once the observation model used in training mismatches the one in test time. In addition, most deep learning methods require vast amounts of training data, which are not accessible in many applications. To mitigate these disadvantages, we propose to combine two image restoration approaches: (i) Deep image Prior (DIP), which trains a convolutional neural network (CNN) from scratch in test time using the given degraded image. It does not require any training data and builds on the implicit prior imposed by the CNN architecture; and (ii) a backprojection (BP) fidelity term, which is an alternative to the standard least squares loss that is usually used in previous DIP works. We demonstrate the performance of the proposed method, termed BP-DIP, on the deblurring task and show its advantages over the plain DIP, with both higher PSNR values and better inference run-time.

关键词： Deep learning Training Training data Tools image restoration Task analysis Electronics packaging

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Stator current signature analysis for fault diagnosis in permanent magnet synchronous wind generators

Stator current signature analysis for fault diagnosis in per...

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International conference on Renewable Energy Research and applications (ICRERA)

作者： A. Del Pizzo L.P. Di Noia D. Lauria R. Rizzo C. Pisani Department of Electrical Engineering and Information Technology University of Napoli Federico II Naples Italy Department of Industrial Engineering University of Napoli Federico II Naples Italy Department of Engineering University of Sannio Benevento Italy

Inter-turn short circuit faults are the most common stator winding faults in permanent magnet wind generators. Their early detection is vital to avoid subsequent damages which can led to catastrophic machine failures. To accomplish this task stator current signature analysis has been recently proposed for identifying inter-turn faults via a non-invasive, non-destructive and cost effective approach. Since no best stator current signature analysis approach is recognized as optimal, the paper takes in consideration the one able to offer the minimum severity degree which is Hilbert Huang Transform. To propose some improvements of the latter in stator current signature analysis, a real 60 kW-25 rpm permanent magnet wind generator is firstly designed via finite element based approach in FLUX® environment. Then SCSA in faulty conditions is performed via proprietary software highlighting how the introduced modifications could further enhance the signal processing algorithm performance.

关键词： Stator windings Lead Reliability wavelet analysis Monitoring Spectral analysis

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Parallel Implementation of 2D-DWT by Purging Read after Write Dependency for High Speed applications

Parallel Implementation of 2D-DWT by Purging Read after Writ...

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International conference on Emerging Technologies, ICET

作者： M. Ashraf M. Shamim Baig Liaqat Ali Khan Ali Hassan Center for Cyber Technology and Spectrum Management National University of Science and Technology Islamabad Pakistan Center for Cyber Technology and Spectrum Management National University of Science and Technology Islamabad

ISBN: (纸本)1424414935

This paper proposes an efficient implementation of multistage, multiple-level DSP algorithms suitable for parallel and distributed processing. To describe our method we selected Mallat's algorithm for two dimensional wavelet transforms (2D-DWT) coefficient computation which has multistage and multilevel processing requirements. We have selected field programmable gate arrays (FPGA) as a processing unit because of its inherited parallel processing capabilities but our method is not limited to FPGAs only. Our method directly computes 2D-DWT coefficients without computing and storing intermediate results; which makes it faster; resource saving and removes read after Write (RAW) dependencies. We discuss multistage and single level implementation but ideally it can be extended to n-level implementation. We also proposed method for generation of "mutually scaled filter coefficients (MSFC)" and computation of maximum number of parallel processors for optimized performance in this particular case. Both lookup tables (LUTs) and multipliers along with addition/subtraction architecture can be used. However, LUTs have advantage of high processing speed. Two computational stages are combined into a single stage to remove read after write (RAW) dependency. Our implementation takes N 2 /4+L 2 /4-2 time units to compute 2D- DWT of N x N input data, with filter length of L without intermediate storage. This method can be used for other multistage, multilevel DSP problems. Quartusreg ii IDE and Altera Stratix device is used for implementation.

关键词： Field programmable gate arrays Table lookup Digital signal processing Filters Distributed processing wavelet transforms Parallel processing Concurrent computing Optimization methods Computer architecture

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Video image processing systems: applications in transportation

Video image processing systems: applications in transportati...

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Vehicle Navigation and Information Systems conference

作者： A. Chatziioanou S.L.M. Hockaday S. Kaighn L. Ponce California Polytechnic State University San Louis Obispo CA USA

California Polytechnic State University, USA, completed an assessment of the potential of using a video image processing (VIP) system for traffic surveillance and detection on California freeways. The first phase of the project, sponsored by the California Department of Transportation, was completed in 1991. Eight turnkey and prototype systems were identified and tested under laboratory conditions. The results showed, that while no system tested was ready for deployment at that time, several systems warranted further testing under more realistic conditions. The second phase of the project began in June 1992 and was completed recently. Four VIP systems were chosen for extended field testing to measure accuracy in traffic counts and speeds, classification, reliability, cost, ease of set-up and operation, image quality, failure rate, and ease of recovery. These variables were assessed quantitatively and qualitatively under specific conditions that included variations of lighting, approaching and departing traffic, camera angle, weather, vibration, and presence of signal noise. This paper presents the Phase ii field test results and recommendations for standardizing image processing systems with a view toward eventual statewide implementation for traffic detection.

关键词： image processing Transportation System testing Surveillance Traffic control Prototypes Laboratories Velocity measurement Costs image quality

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