检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

10 篇 会议

馆藏范围

10 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

9 篇 工学
- 7 篇 电子科学与技术（可...
- 7 篇 计算机科学与技术...
- 4 篇 轻工技术与工程
- 3 篇 材料科学与工程（可...
- 2 篇 光学工程
- 2 篇 化学工程与技术
- 1 篇 冶金工程
- 1 篇 电气工程
- 1 篇 土木工程
- 1 篇 生物医学工程（可授...
- 1 篇 软件工程
- 1 篇 生物工程
3 篇 理学
- 2 篇 数学
- 1 篇 物理学
- 1 篇 生物学
1 篇 经济学
- 1 篇 应用经济学
1 篇 管理学
- 1 篇 管理科学与工程(可...
- 1 篇 工商管理

主题

2 篇 computer circuit...
1 篇 design rules
1 篇 metals
1 篇 failure analysis
1 篇 fabrication
1 篇 transistors
1 篇 graphics process...
1 篇 resistance
1 篇 design
1 篇 silicon
1 篇 photoresists
1 篇 epitaxy
1 篇 fin field effect...
1 篇 back end of line
1 篇 inspection
1 篇 cells
1 篇 nanosheets

机构

3 篇 siemens eda 8005...
3 篇 imec kapeldreef ...
3 篇 siemens eda 4689...
2 篇 siemens eda 110 ...
2 篇 siemens eda inte...
2 篇 carl zeiss smt g...
1 篇 the chinese univ...
1 篇 logic technology...
1 篇 institute of mic...
1 篇 siemens eda 5000...
1 篇 asml brion 80 we...
1 篇 kla corporation ...
1 篇 nvidia crop unit...
1 篇 university of ch...
1 篇 guangdong greate...
1 篇 asml technology ...
1 篇 katholieke unive...
1 篇 siemens eda 4-7-...

作者

3 篇 lafferty neal
3 篇 zhang xima
2 篇 armeanu ana-mari...
2 篇 fenger germain
2 篇 sears monica kem...
2 篇 zimmermann joerg
2 篇 lee jeonghoon
2 篇 gillijns werner
2 篇 wei chih i.
2 篇 malankin evgeny
1 篇 aykol m.
1 篇 gao weimin
1 篇 zhang z.
1 篇 catthoor francky
1 篇 trivkovic darko
1 篇 xiang yang
1 篇 tien ming-chun
1 篇 mizuuchi keisuke
1 篇 maguire ethan
1 篇 tang jialei

语言

10 篇 英文

检索条件"任意字段=DTCO and Computational Patterning II 2023"

共 10 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

dtco and computational patterning ii

DTCO and Computational Patterning II

引用

dtco and computational patterning ii 2023

ISBN: (纸本)9781510660977

The proceedings contain 56 papers. The topics discussed include: full chip inverse lithography technology mask synthesis for advanced memory manufacturing;structured assist features in inverse lithography;curvilinear data representation and its impact on file size and lithographic performance;probability model of bridging defects for random logic via in 3nm double patterning technology at 0.33 NA;next-generation logic design architecture for vertical-transport nanosheets;modeling accuracy and tat improvements for next generation mask error correction;patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing;methodology development to benchmark power delivery designs in advanced technology nodes;electrical analysis of a stochastically simulated 2 nm node electrical test structure;and scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis.

关键词：

来源：评论

学校读者我要写书评

暂无评论

dtco of sequential and monolithic CFET SRAM 2

DTCO of sequential and monolithic CFET SRAM

引用

dtco and computational patterning ii 2023

作者： Liu, Hsiao-Hsuan Salahuddin, Sharife M. Chan, Boon Teik Schuddinck, Pieter Xiang, Yang Weckx, Pieter Hellings, Geert Catthoor, Francky Imec Kapeldreef 75 Leuven3001 Belgium Katholieke Universiteit Leuven Leuven3000 Belgium

ISBN: (纸本)9781510660977

Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions. © 2023 SPIE.

关键词： Fin field effect transistors Back end of line Silicon Design rules Metals Epitaxy Fabrication Resistance Transistors Nanosheets

来源：评论

学校读者我要写书评

暂无评论

GPU-Accelerated Matrix Cover Algorithm for Multiple patterning Layout Decomposition 2

GPU-Accelerated Matrix Cover Algorithm for Multiple Patterni...

引用

dtco and computational patterning ii 2023

作者： Chen, Guojin Yang, Haoyu Yu, Bei The Chinese University of Hong Kong NT Hong Kong NVIDIA Crop United States

ISBN: (纸本)9781510660977

Multiple patterning lithography (MPL) is regarded as one of the most promising ways of overcoming the resolution limitations of conventional optical lithography due to the delay of next-generation lithography technology. As the feature size continues to decrease, layout decomposition for multiple patterning lithography (MPLD) technology is becoming increasingly crucial for improving the manufacturability in advanced nodes. The decomposition process refers to assigning the layout features to different mask layers according to the design rules and density requirements. When the number of masks k ≥ 3, the MPLD problems are NP-hard and thus may suffer from runtime overhead for practical designs. However, the number of layout patterns is increasing exponentially in industrial layouts, which hinders the runtime performance of MPLD models. In this research, we substitute the CPU's dance link data structure with parallel GPU matrix operations to accelerate the solution for exact cover-based MPLD algorithms. Experimental results demonstrate that our system is capable of full-scale, lightning-fast layout decomposition, which can achieve more than 10× speed-up without quality degradation compared to state-of-the-art layout decomposition methods. © 2023 SPIE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Probability model of bridging defects for random logic via in 3nm double patterning technology at 0.33 NA 2

Probability model of bridging defects for random logic via i...

引用

dtco and computational patterning ii 2023

作者： Su, Xiaojing Li, Jingjing Fan, Taian Wang, Jiashuo Dong, Lisong Su, Yajuan Wei, Yayi Institute of Microelectronics The Chinese Academy of Sciences Beijing10029 China University of Chinese Academy of Sciences Beijing10049 China Guangdong Greater Bay Area Institute of Integrated Circuit and System Building A No. 136 Kaiyuan Avenue Guangzhou510535 China

ISBN: (纸本)9781510660977

Extreme ultraviolet (EUV) double patterning (DP) with a numeric aperture (NA) of 0.33 can be introduced for the critical via layers at 3nm logic node. The minimum center to center (C2C) distance of a via pattern may form bridging defects even adopting EUV DP. The implemented via process, pattern shifts induced by EUV illuminator, overlay capability and OPC strategies may lead to bridging defects in EUV DP process. This paper will put forth a compact model to detect potential bridging hotspots and predict the corresponding probability of failure considering aforementioned process variations. The feasible design, patterning solutions, and process parameters can be optimized and compensated quantitatively to avoid design updates and mask rebuild. © 2023 SPIE.

关键词： Failure analysis

来源：评论

学校读者我要写书评

暂无评论

computational lithography solutions to support EUV High-NA patterning 2

Computational lithography solutions to support EUV High-NA p...

引用

dtco and computational patterning ii 2023

作者： Zhao, Rongkuo Zhou, Fan Tang, Jialei Lu, Jeff Liu, Yunbo Sun, Dezheng Tien, Ming-Chun Hsu, Stephen Gupta, Rachit Zhang, Youping Zimmermann, Joerg ASML Brion 80 West Tasman San JoseCA95131 United States Carl Zeiss SMT GmbH

ISBN: (纸本)9781510660977

The EUV High-NA scanner brings innovative design changes to projection optics, such as introducing center obscuration and the anamorphic projection optical system in the projection optics box (POB) to improve the system transmission while the NA is improved1. These design changes need to be accounted for in the computational lithography software solutions, to ensure accurate modeling and optimization of the High-NA system performance on wafer. In this paper, we will systematically investigate the benefits of Source Mask Optimization (SMO) and mask only optimization to explore EUV High-NA full chip patterning solutions, where mask 3D effects (M3D) are captured in the optical modeling. The paper will focus on assessing the performance (including process window, depth of focus, normalized image log slope) of through-pitch 1D Line/space (L/S) patterns and 2D Contact/Hole (CH) patterns after aforementioned optimizations and demonstrate the impact of center obscuration on imaging. In addition, we will investigate the effect of sub-resolution assistant feature (SRAF) on High-NA patterning via comparing the optimized lithographic performance with and without SRAF. These findings will help determine the most optimal patterning solutions for EUV High-NA as we move towards the first High NA EUV insertion. The paper will also discuss the anamorphic SMO where MRC and mask description needs to change from wafer plane (1x1) to scaled reticle plane (1x2). The interfield stitching will also be briefly discussed in this paper. © 2023 SPIE.

关键词： Design

来源：评论

学校读者我要写书评

暂无评论

patterning Assessment Using 0.33NA EUV Single Mask for Next Generation DRAM Manufacturing 2

Patterning Assessment Using 0.33NA EUV Single Mask for Next ...

引用

dtco and computational patterning ii 2023

作者： Lee, Jeonghoon Halder, Sandip Pham, Van Tuong Fallica, Roberto Heo, Seonggil Sah, Kaushik Suh, Hyo Seon Blanco, Victor Gillijns, Werner Cross, Andrew Maguire, Ethan Armeanu, Ana-Maria Liubich, Vladislav Malankin, Evgeny Zhang, Xima Sears, Monica Kempsell Lafferty, Neal Fenger, Germain Wei, Chih I. Kim, Ryoung Han Imec Kapeldreef 75 Leuven3001 Belgium KLA Corporation One Technology Drive MilpitasCA95035 United States Siemens EDA 110 rue Blaise Pascal Montbonnot Saint Martin38330 France Siemens EDA 46897 Bayside Pkwy FremontCA United States Siemens EDA 8005 SW Boeckman Rd WilsonvilleOR United States Siemens EDA Interleuvenlaan 68 Leuven3001 Belgium

ISBN: (纸本)9781510660977

This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC. © 2023 SPIE.

关键词： Inspection

来源：评论

学校读者我要写书评

暂无评论

Application of Resolution Enhancement Techniques at High NA EUV for Next Generation DRAM patterning 2

Application of Resolution Enhancement Techniques at High NA ...

引用

dtco and computational patterning ii 2023

作者： Armeanu, Ana-Maria Malankin, Evgeny Lafferty, Neal Wei, Chih I. Sears, Monica Kempsell Fenger, Germain Zhang, Xima Gillijns, Werner Trivkovic, Darko Kim, Ryoung-Han Lee, Jeonghoon Siemens EDA 110 rue Blaise Pascal Montbonnot Saint Martin38330 France Siemens EDA 8005 SW Boeckman Rd WilsonvilleOR United States Siemens EDA Interleuvenlaan 68 Leuven3001 Belgium Siemens EDA 46897 Bayside Pkwy FremontCA United States IMEC Kapeldreef 75 Leuven3001 Belgium

ISBN: (纸本)9781510660977

Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (dtco) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the

关键词： Cells

来源：评论

学校读者我要写书评

暂无评论

Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node 2

Direct print EUV patterning of tight pitch metal layers for ...

引用

dtco and computational patterning ii 2023

作者： Venkatesan, R. Guven, C. Bhawe, D. Greenwood, A.R. Zhang, Z. Gupta, P. Saksena, P. Rodriguez, R. Moumen, N. Bains, B. Sun, P. Aykol, M. Wallace, C. Bigwood, R. Fischer, K. Logic Technology Development Intel Corporation 2501 NE Century Blvd HillsboroOR97124 United States

ISBN: (纸本)9781510660977

This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of ~30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers. Careful co-optimization of the illumination source, photoresist and lithography stack is essential to resolve the tightest pitches. Optimum CDSEM metrology conditions and EUV specific requirements such as full field correction with thru slit, flare and black border compensation are critical to improve the quality of the optical proximity correction (OPC) flows. OPC algorithms were used to maximize the process window by using width sizing and pitch shifting to meet lithographic printability criteria while pushing mask manufacturability constraints to their healthy limits. The sizing of metal lines is modelled and fed to the RC extraction flows to close the fab-design house feedback loop to improve accuracy of timing closure. A novel directional etch process enabled the direct print patterning of line tip-to-tips without requiring a second blocking mask. Multiple test masks were specifically designed to increase sensitivity of defect metrology and accelerate yield learning. Our results from multiple product vehicles demonstrate achievement of technology readiness milestones. © 2023 SPIE.

关键词： Photoresists

来源：评论

学校读者我要写书评

暂无评论

EUV full-chip curvilinear mask options for logic via and metal patterning 2

EUV full-chip curvilinear mask options for logic via and met...

引用

dtco and computational patterning ii 2023

作者： Lafferty, Neal Saxena, Sagar Mizuuchi, Keisuke Ma, Yuansheng Zhang, Xima LaCour, Pat Tritchkov, Alexander Kmiec, Farah Sturtevant, John Siemens EDA 8005 SW Boeckman Rd WilsonvilleOR United States Siemens EDA 4-7-35 Kita-Shinagawa Tokyo Japan Siemens EDA 46897 Bayside Pkwy FremontCA United States Siemens EDA 5000 Plaza On The Lake AustinTX United States

ISBN: (纸本)9781510660977

With the adoption of multi-beam mask writing (MBMW) technology, there is a strong drive to realize the maximum lithographic process window entitlement which can be obtained with curvilinear masks, including both SRAFs and main features. Inverse Lithography Technology (ILT) has always featured prominently in planning for such masks, as it can produce the ideal curvilinear patterns which represent the best possible solution. The runtime for ILT, however, remains too slow for full-chip logic manufacturing and this paper will review multiple alternative approaches which endeavor to produce similar output masks but with significantly faster runtime. Results will be shown for 3nm-node via and metal examples where full ILT, hybrid ILT & dense curvilinear OPC, hybrid curvilinear SRAF & dense curvilinear OPC, and machine learning approaches will be assessed for runtime and a variety of lithographic metrics. Overall, all solutions are shown to be considerably faster than full ILT, ranging between 4x (for hybrid ILT SRAF) to >100X improved runtime performance. Lithographic capability is characterized in terms of distributions of edge placement errors (EPE), PV Bands, and ILS/NILS. There are some minor differences between the various options, but given the pronounced runtime advantages over ILT, all are compelling options, delivering lithographic PW enablement close to the ideal ILT solution. For the model-based DNN, and Monotonic Machine Learning (MML) approaches, we will discuss the approach, challenges, and advantages associated with robust training to ensure the broadest possible pattern coverage. © 2023 SPIE.

关键词： Computer circuits

来源：评论

学校读者我要写书评

暂无评论

computational evaluation of critical logic metal layers of pitch 20-24nm and aberration sensitivity in high NA EUV single patterning 2

Computational evaluation of critical logic metal layers of p...

引用

dtco and computational patterning ii 2023

作者： Gao, Weimin Chen, Chun-Kuang Zimmermann, Joerg ASML Technology Development Center Carl Zeiss SMT GmbH

ISBN: (纸本)9781510660977

As chip manufacturers seek to reduce the pitch of metal layers, there is growing interest in replacing the multiple patterning process of 0.33NA EUV with a single patterning of high NA (0.55NA) EUV. However, to resolve a logic metal layout with a minimum pitch of 20-24nm, careful use of resolution enhancement techniques (RETs) and SMO (source mask optimization) is required in high NA EUV. Logic metal patterns are complex and have various feature designs, making it essential to ensure sufficient patterning performance across all pitches and for variations of tip-to-tip (T2T) structures with a tight size. In this study, we simulated and evaluated patterning on a typical logic metal layout representing 1.4nm to 1nm technology nodes. Our study demonstrates that compromised criteria are necessary to ensure the NILS (normalized image log-slope) level of the minimum pitch and the overlap critical dimension (CD) process window (PW). In optical proximity correction (OPC), sub-resolution assistant features (SRAF) help to improve the process window of isolated and semi-iso line-and-space (L/S) patterns. However, we found that the limiting patterns are the tight T2T structures. Aberration sensitivity showed a linear response that is more pronounced to pattern placement errors (PPE) than to CDs. The coma series aberration showed the highest sensitivity to PPE and CD. Overall, our study demonstrates that RETs, rigorous SMO solutions, and a minimum T2T size are required to achieve the replacement of 0.33NA EUV multi-patterning with a 0.55NA EUV single patterning (SP) for logic metal layers with minimum pitches of 20-24nm. © 2023 SPIE.

关键词： Computer circuits

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共1页 << < 1 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：