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Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Verilua: An Open Source Versatile Framework for Efficient Ha...

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design, automation and test in europe conference and exhibition

作者： Ye Cai Chuyu Zheng Wei He Dan Tang College of Computer Science and Software Engineering Shenzhen University Shenzhen China Beijing Institute of Open Source Chip Beijing China Institute of Computing Technology Chinese Academy of Sciences (lCT) Beijing China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The growing complexity of hardware verification highlights limitations in existing frameworks, particularly regarding flexibility and reusability. Current methodologies often require multiple specialized environments for functional verification, waveform analysis, and simulation, leading to toolchain fragmentation and inefficient code reuse. This paper presents Verilua, a unified framework leveraging LuaJIT and the Verilog Procedural Interface (VPI), which integrates three core functional-ities: Lua-based functional verification, a scripting engine for RTL simulation, and waveform analysis. By enabling complete code reuse through a unified Lua codebase, the framework achieves a 12x speedup in RTL simulation compared to cocotb and a 70x improvement in waveform analysis over state-of-the-art solutions. Through consolidating verification tasks into a single platform, Verilua enhances efficiency while reducing tool fragmentation and learning overhead, addressing critical challenges in modern hardware design.

关键词： Codes europe Hardware Complexity theory Signal analysis Hardware design languages Engines

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Timing-Driven Global Placement With Hybrid Heuristics and Nadam-Based Net Weighting

Timing-Driven Global Placement With Hybrid Heuristics and Na...

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design, automation and test in europe conference and exhibition

作者： Linhao Lu Wenxin Yu Hongwei Tian Chenjin Li Xinmiao Li Zhaoqi Fu Zhengjie Zhao Jingwei Lu Southwest University of Science and Technology Mianyang Sichuan China TikTok

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Timing optimization is critical to the entire design flow of the very-large-scale integrated (VLSI) circuit, and Global Placement is pivotal in achieving timing closure within the design flow of very-large-scale integration circuits. However, most global placement algorithms focus on optimizing wirelength rather than timing. Therefore, we propose a novel timing-driven global placement algorithm to address this gap. This paper proposes a timing-driven global placement algorithm utilizing a Nadam-based net-weighting strategy. Additionally, we employ a hybrid heuristic approach for adaptive dynamic adjustment of net weights. The experimental results on the ICCAD 2015 contest benchmarks show that compared to the RePlAce, our algorithm significantly improves WNS and TNS by 40.7% and 56.5%, respectively.

关键词： Runtime Heuristic algorithms europe Very large scale integration Benchmark testing Timing Optimization Convergence Investment

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Poros: One-Level Architecture-Mapping Co-Exploration for Tensor Algorithms

Poros: One-Level Architecture-Mapping Co-Exploration for Ten...

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design, automation and test in europe conference and exhibition

作者： Fuyu Wang Minghua Shen School of Computer Science and Engineering Sun Yat-Sen University Guangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Tensor algorithms increasingly rely on specialized accelerators to meet growing performance and efficiency demands. Given the rapid evolution of these algorithms and the high cost of designing accelerators, automated solutions for jointly optimizing both architectures and mappings have gained attention. However, the joint design space is non-convex and non-smooth, hindering the finding of optimal or near-optimal designs. Moreover, prior work conducts two-level exploration, resulting in a combinatorial explosion. In this paper, we propose Poros, a one-level architecture-mapping co-exploration framework. Poros directly explores a batch of architecture-mapping configurations and evaluates their performance. It then exploits reinforcement learning to perform gradient-based search in the non-smooth joint design space. By sampling from the policy, Poros keeps exploring new actions to address non-convexity. Experimental results demonstrate that Poros achieves up to 5.32 × and 2.15 × better EDP compared with hand-designed accelerators and state-of-the-art automatic approaches respectively. Through one-level exploration scheme, Poros also converges at least 20% faster than other approaches.

关键词： Gradient methods Tensors Costs europe Reinforcement learning Explosions Neural architecture search

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Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)

Multi-Partner Project: Twinning for Excellence in Reliable E...

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design, automation and test in europe conference and exhibition

作者： Marko Andjelkovic Fabian Vargas Milos Krstic Luigi Dilillo Alain Michez Frederic Wrobel Davide Bertozzi Mikel Lujan Christos Georgakidis Nikolaos Chatzivangelis Katerina Tsilingiri Nikolaos Zazatis Georgios Ioanis Paliaroutis Pelopidas Tsoumanis Christos Sotiriou IHP - Leibniz-Institut für innovative Mikroelektronik Frankfurt (Oder) Germany University of Potsdam Potsdam Germany CNRS - Centre National de la Recherche Scientifique Montpellier France Institut d 'Electronique et des Systèmes (IES) Montpellier France University of Montpellier Montpellier France University of Manchester Manchester United Kingdom University of Thessaly Volos Greece

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Reliable electronics plays a major role in shaping our daily lives, being a key enabler for critical applications, such as space missions, avionics, automotive, medicine, banking, automated industry, wireless communication networks, etc. However, design of highly reliable electronic systems remains a challenge with the advances in semiconductor technology and increase in integrated circuit (IC) complexity. In this work, we introduce the Horizon europe Twinning project TWIN-RELECT, aimed at strengthening the scientific expertise in designing reliable integrated circuits. The paper presents the general project concept and objectives, and main directions of the joint research activities. The primary scientific goal is to contribute to the development of novel, more efficient, european Electronic design automation (EDA) tool-chain for design of reliable chips.

关键词： Integrated circuits Wireless communication Industries design automation Space missions europe Reliability engineering Circuit faults Integrated circuit reliability Transient analysis

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Word-Level Counterexample Reduction Methods for Hardware Verification

Word-Level Counterexample Reduction Methods for Hardware Ver...

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design, automation and test in europe conference and exhibition

作者： Zhiyuan Yan Hongce Zhang Microelectronics Thrust The Hong Kong University of Science and Technology (Guangzhou)

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Hardware verification is crucial to ensure the cor-rectness in the logic design of digital circuits. The purpose of verification is to either find bugs or show their absence. Prior works mostly focus on the bug-finding process and have proposed a range of verification algorithms and techniques to be faster to reach a bug or conclude with a proof of correctness. However, for a human verification engineer, it also matters how to better analyze the counterexamples trace to understand the root cause of bugs. This kind of technique remains absent in word-level circuit analysis. In this paper, we investigate the counterexample reduction method. Given the existing techniques for the bit-level circuit model, we first extend current semantic analysis methods to the word-level counterexample reduction and then develop a more efficient word-level structural analysis approach. We compare the effectiveness and overhead of these methods on the hardware model-checking problems and show the usefulness of such analysis in applications including pivot input analysis, word-level model-checking and counterexample-guided abstraction refinement.

关键词： Analytical models Computer bugs Semantics europe Model checking Hardware Logic design Integrated circuit modeling Circuit analysis Digital circuits

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SMT-Based Repairing Real-Time Task Specifications

SMT-Based Repairing Real-Time Task Specifications

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design, automation and test in europe conference and exhibition

作者： Anand Yeolekar Ravindra Metta Samarjit Chakraborty TCS Research India TUM Germany Dept. of CS UNC Chapel Hill USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

When addressing timing issues in real-time systems, approaches for systematic timing debugging and repair have been missing due to (i) Lack of available feedback: most timing analysis techniques, being closed-form analytical techniques, are unable to provide root cause information when a timing property is violated, which is critical for identifying an appropriate repair, and (ii) Pessimism in the analysis: existing schedulability analysis techniques tend to make worst case assumptions in the presence of non-determinism introduced by real-world factors such as release jitter, or sporadic tasks. To address this gap, we propose an SMT encoding of task runs for exact debugging of timing violations, and a procedure to iteratively repair a given task specification. We demonstrate the utility of this procedure by repairing example task sets scheduled under global non-preemptive earliest-deadline-first scheduling, a common choice for many safety-critical systems.

关键词： Systematics europe Debugging Maintenance engineering Jitter Real-time systems Encoding Timing

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ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering

ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering

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design, automation and test in europe conference and exhibition

作者： Lizi Zhang Azadeh Davoodi Rasit Onur Topaloglu University of Wisconsin-Madison Madison USA Adeia Inc. Poughkeepsie NY USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In this paper, we introduce ReBERT, a specialized large language model (LLM) based on BERT, fine-tuned specifically for grouping bits into words within gate-level netlists. By treating the netlist as a form of language, we encode bits and their fan-in cones into sequences that capture structural dependencies. A novel contribution is augmenting BERT's embedding with a tree-based embedding strategy which mirrors the hierarchical nature of circuit designs in hardware. Leveraging the powerful representational learning capabilities of LLMs, we interpret hardware circuits at a higher level of abstraction. We evaluate ReBERT on various hardware designs, demonstrating that it significantly outperforms a state-of-the-art work based on partial structural matching in recovering word-level groupings. Our improvements are on average between 12.2% to 218.1% depending on degree of corrupting the structural patterns.

关键词： Large language models Reverse engineering europe Logic gates Reliability engineering Hardware Robustness Encoding Mirrors Integrated circuit reliability

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One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs

One Gray Code Fits All: Optimizing Access Time with Bi-Direc...

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design, automation and test in europe conference and exhibition

作者： Shaoqi Li Tianyu Wang Yongbiao Zhu Chenlin Ma Yi Wang Zhaoyan Shen Zili Shao College of Computer Science and Software Engineering Shenzhen University Shenzhen China School of Computer Science and Technology Shandong University Qingdao China Department of Computer Science and Engineering The Chinese University of Hong Kong Hong Kong China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Gray code, a voltage-level-to-data-bit translation scheme, is widely used in QLC SSDs. However, it causes the four data bits in QLC to exhibit significantly different read and write performance with up to 8 × latency variation, severely impacting the worst-case performance of QLC SSDs. This paper presents BDP, a novel Bi-Directional Programming scheme. Based on a fixed Gray code, BDP combines both the normal (forward) and reverse programming directions to enable runtime programming direction arbitration. Experimental results show that BDP can effectively improve the read and write performance of SSD compared to representative schemes.

关键词： Translation Runtime europe Bidirectional control Programming Reflective binary codes

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Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries

Enabling a Portable Brain Computer Interface for Rehabilitat...

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design, automation and test in europe conference and exhibition

作者： Adrian Evans Victor Roux-Sibillon Joe Saad Ivan Miro-Panades Tetiana Aksenova Lorena Anghel Univ. Grenoble Alpes CEA LIST Grenoble France Univ. Grenoble Alpes CEA LETI Grenoble France Univ. Grenoble Alpes CNRS Grenoble INP Grenoble France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In clinical trials, brain signal decoders combined with spinal stimulation have shown to be a promising means to restore mobility to paraplegic and tetraplegic patients. To make this technology available for home use, the complex brain signal decoding must be performed using a low-power, portable battery operated system. This case study shows how the decoding algorithm for a Brain-Computer Interface (BCI) system was ported to an embedded platform, resulting in an over 25 x power reduction, compared to the previous implementation, while respecting real-time and accuracy constraints.

关键词： Integrated circuits europe Implants Motors Feature extraction Brain-computer interfaces Real-time systems Decoding Spinal cord injury Optimization

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EF-IMR: Embedded Flash with Interlaced Magnetic Recording Technology

EF-IMR: Embedded Flash with Interlaced Magnetic Recording Te...

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design, automation and test in europe conference and exhibition

作者： Chenlin Ma Xiaochuan Zheng Kaoyi Sun Tianyu Wang Yi Wang College of Computer Science and Software Engineering Shenzhen University China State Key Laboratory of Radio Frequency Heterogeneous Integration

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Interlaced Magnetic Recording (IMR), a technology that improves storage density through track overlap, introduces significant latency due to Read-Modify-Write (RMW) operations. Writing to overlapped tracks affects underlying tracks, requiring additional I/O operations to read, back up, and rewrite them, resulting in significant head movement latency. We propose EF-IMR, a new architecture that ensures crash consistency in IMR while minimizing RMW latency and head movement. EF-IMR reduces head movement during RMW operations and decreases redundant RMW operations. Evaluations under real-world, intensive I/O workloads show that EF-IMR reduces RMW latency by 20.11 % and head movement latency by 89.37% compared to existing methods.

关键词： Tracking europe Writing Magnetic heads Computer crashes Delays Magnetic recording

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