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Algorithm-Hardware Co-design of a Unified Accelerator for Non-Linear Functions in Transformers

Algorithm-Hardware Co-Design of a Unified Accelerator for No...

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design, automation and test in europe conference and exhibition

作者： Haonan Du Chenyi Wen Zhengrui Chen Li Zhang Qi Sun Zheyu Yan Cheng Zhuo Zhejiang University Hubei University Of Technology

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Nonlinear functions (NFs) in Transformers require high-precision computation consuming significant time and energy, despite the aggressive quantization schemes for other components. Piece-wise Linear (PWL) approximation-based methods offer more efficient processing schemes for NFs but fall short in dealing with functions with high nonlinearities. Moreover, PWL-based methods still suffer from inevitably high latency introduced by the Multiply-And-Add (MADD) unit. To address these issues, this paper proposes a novel quadratic approximation scheme and a highly integrated, multiplier-less hardware structure, as a unified method to accelerate any unary nonlinear function. We also demonstrate implementation examples for GELU, Softmax, and LayerNorm. The experimental results show that the proposed method achieves up to 5.41% higher inference accuracy and 60.12% lower area-delay product.

关键词： Accuracy Quantization (signal) Computational modeling europe Life estimation Transformers Approximation algorithms Hardware Inference algorithms Integrated circuit modeling

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Late Breaking Results: Automatic Anomaly Detection Method in Physical Unclonable Functions using Data Mining Techniques

Late Breaking Results: Automatic Anomaly Detection Method in...

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design, automation and test in europe conference and exhibition

作者： Mohammad Reza Heidari Iman Sergio Vinagrero Gutierrez Elena-Ioana Vatajelu Giorgio Di Natale Univ. Grenoble Alpes CNRS Grenoble INP* TIMA Grenoble France Institut des Nanotechnologies de Lyon (INL)

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Physical Unclonable Functions (PUFs) present a promising alternative to traditional cryptographic techniques for securing sensitive information in modern circuits. By exploiting inherent process variability, PUFs generate unique secrets dynamically, thus eliminating the need for data storage. However, a major challenge in PUF-based security is distinguishing valid PUFs from those that may have been tampered with or are invalid (i.e., not belonging to the original design). This paper proposes a data mining-based approach for detecting anomalies and identifying tampered or invalid PUFs. The proposed method mines a set of rules that describe the expected behavior of the PUF, with deviations from these rules signaling potential security issues and vulnerabilities. Experimental results demonstrate that the method effectively identifies invalid or tampered PUFs, showcasing its potential for enhancing PUF-based security systems.

关键词： Circuits Memory europe Physical unclonable function Cryptography Anomaly detection

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ChipVQA: Benchmarking Visual Language Models for Chip design

ChipVQA: Benchmarking Visual Language Models for Chip Design

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design, automation and test in europe conference and exhibition

作者： Haoyu Yang Qijing Huang Nathaniel Pinckney Walker Turner Wenfei Zhou Yanqing Zhang Chia-Tung Ho Chen-Chia Chang Haoxing Ren NVIDIA Corp.

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Large-language models (LLMs) have exhibited great potential to assist chip designs and analysis. Recent research and efforts are mainly focusing on text-based tasks including general QA, debugging, design tool scripting, and so on. However, chip design and implementation workflow usually require a visual understanding of diagrams, flow charts, graphs, schematics, waveforms, etc, which demands the development of multimodality foundation models. In this paper, we propose ChipVQA, a benchmark designed to evaluate the capability of visual language models for chip design. ChipVQA includes 142 carefully designed and collected VQA questions covering five chip design disciplines: Digital design, Analog design, Architecture, Physical design and Semiconductor Manufacturing. Unlike existing VQA benchmarks, ChipVQA questions are carefully designed by chip design experts and require indepth domain knowledge and reasoning to solve. We conduct comprehensive evaluations on both open-source and proprietary multimodal models that are greatly challenged by the benchmark suit. ChipVQA is available at https://***/phdyang007/chipvqa.

关键词： Training Visualization Foundation models Focusing europe Benchmark testing Semiconductor device manufacture Problem-solving Chip scale packaging Physical design

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Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based test Generation

Comprehensive RISC- V Floating-Point Verification: Efficient...

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design, automation and test in europe conference and exhibition

作者： Tianyao Lu Anlin Liu Bingjie Xia Peng Liu College of Information Science and Electronic Engineering Zhejiang University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The increasing complexity of processor architectures necessitates more rigorous functional verification. Floating-point operations, in particular, present significant challenges due to their extensive range of computational cases that require verification. This paper proposes a comprehensive approach for generating floating-point instruction sequences to enhance the verification of RISC-V. We introduce a constraint-based method for floating-point test generation and design efficient coverage models as input constraints for this process. The resulting representative floating-point tests are integrated with RISC-V instruction sequence generation through a memory-bound register update method. Experimental results demonstrate that our approach improves the functional coverage of RISC-V floating-point instruction sequences from 93.32% to 98.34%, while simultaneously reducing the number of required instructions by 66.67% compared to the Google RISCV-DV generator. Additionally, our method achieves more comprehensive coverage of floating-point types in instruction write-back data compared to RISCV-DV. Using the proposed approach, we successfully detect representative floating-point-related faults injected into the RISC-V processor CV32E40P, thereby demonstrating its effectiveness.

关键词： Computational modeling Diversity reception Computer bugs europe Computer architecture Generators Registers Internet test pattern generators Reliability

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Bias by design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic Optimization

Bias by Design: Diversity Quantification to Mitigate Structu...

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design, automation and test in europe conference and exhibition

作者： Isabella Venancia Gardner Marcel Walter Yukio Miyasaka Robert Wille Michael Cochez Universiteit van Amsterdam Netherlands Vrije Universiteit Amsterdam Netherlands Chair for Design Automation Technical University of Munich Germany University of California Berkeley USA Software Competence Center Hagenberg GmbH (SCCH) Austria

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

And-Inverter Graphs (AIGs) are a fundamental data structure in logic optimization, widely used in modern electronic design automation. A persistent challenge in AIG optimization is structural bias, where the initial graph structure strongly influences optimization quality by restricting the search space, often resulting in subpar outcomes. Existing methods address this issue by running multiple optimization workflows in parallel, relying on a trial-and-error approach that lacks a systematic way to measure structural diversity or assess effectiveness, making them computationally expensive and inefficient. This paper introduces a novel framework for systematically evaluating and reducing structural bias by measuring structural diversity, defined as the degree of dissimilarity between AIG graphs. Several traditional graph similarity measures and newly proposed AIG-specific metrics, including the Rewrite, Refactor, and Resub Scores, are explored. Results reveal limitations in traditional graph similarity metrics and highlight the effectiveness of the proposed AIG-specific measures in quantifying structural dissimilarity. Notably, the RRR Score shows a strong correlation (Pearson correlation coefficient, $r$ = 0.79) with post-optimization structural differences, demonstrating the reliability of the metric in capturing meaningful variations between AIG structures. This work addresses the challenge of quantifying structural bias and offers a methodology that can potentially improve optimization outcomes, with future extensions applicable to other logic graph types.

关键词： Measurement Systematics Correlation europe Data structures Logic design Graph theory Logic Reliability Optimization

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Multi-Partner Project: Advancing the EDA Tools Landscape for the european RISC-V Ecosystem in TRISTAN

Multi-Partner Project: Advancing the EDA Tools Landscape for...

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design, automation and test in europe conference and exhibition

作者： Fatma Jebali Caaliph Andriamisaina Mathieu Jan Wolfgang Ecker Florian Egert Bernhard Fischer Alessio Burrello Daniele Jahier Pagliari Sara Vinco Giuseppe Tagliavini Ingo Feldner Andreas Mauderer Axel Sauer Arnór Kristmundsson Alexander Schober Téo Bernier Matti Käyrä Ulf Schlichtmann Rocco Jonack Université Paris-Saclay CEA List Palaiseau France Infineon Technologies AG Siemens Foundational Technology Vienna Austria Politecnico di Torino Italy University of Bologna Italy Robert Bosch GmbH Germany Codasip GmbH Germany Thales Research & Technology France Tampere University Finland Technical University of Munich Germany MINRES Technologies GmbH Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The TRISTAN project aims to expand and industrialize the european RISC-V ecosystem to compete effectively with existing commercial alternatives. This initiative specifically targets the critical challenges in the development of Electronic design automation (EDA) tools, essential for RISC-V-based solutions, by leveraging the synergy between the open-source community and industrial solutions. This paper presents an overview of the current landscape of TRISTAN's EDA flow, highlighting specific tools and methodologies that streamline the early design phases of RISC-V-based systems. We explore the unique features of these tools, emphasizing how they complement each other to strengthen the overall design process.

关键词： design automation Ecosystems europe Reliability engineering Research and development Interoperability

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SEGA-DCIM: design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support

SEGA-DCIM: Design Space Exploration-Guided Automatic Digital...

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design, automation and test in europe conference and exhibition

作者： Haikang Diao Haoyi Zhang Jiahao Song Haoyang Luo Yibo Lin Runsheng Wang Yuan Wang Xiyuan Tang Peking University Beijing China University of California San Diego CA USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Digital computing-in-memory (DCIM) has been a popular solution for addressing the memory wall problem in recent years. However, the DCIM design still heavily relies on manual efforts, and the optimization of DCIM is often based on human experience. These disadvantages limit the time to market while increasing the design difficulty of DCIMs. This work proposes a design space exploration-guided automatic DCIM compiler (SEGA-DCIM) with multiple precision support, including integer and floating-point data precision operations. SEGA-DCIM can automatically generate netlists and layouts of DCIM designs by leveraging a template-based method. With a multi-objective genetic algorithm (MOGA)-based design space explorer, SEGA-DCIM can easily select appropriate DCIM designs for a specific application considering the trade-offs among area, power, and delay. As demonstrated by the experimental results, SEGA-DCIM offers solutions with wide design space, including integer and floating-point precision designs, while maintaining competitive performance compared to state-of-the-art (SOTA) DCIMs.

关键词： Hands Layout Time to market europe Manuals In-memory computing Robustness Space exploration Optimization Genetic algorithms

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Multi-Partner Project: Shaping the Vehicle of the Future - How FEDERATE and HAL4SDV are Steering europe's Software-Defined Vehicle Ecosystem

Multi-Partner Project: Shaping the Vehicle of the Future - H...

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design, automation and test in europe conference and exhibition

作者： Michael Paulweber Andreas Eckel Paolo Azzoni AVL Gratz Austria TTTech Computertechnik AG Vienna Austria INSIDE Industry Association Eindhoven The Netherland

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The FEDERATE and HAL4SDV projects aim to address the growing importance of software in the automotive industry, positioning europe as a leader in the software-defined vehicle (SDV) domain. FEDERATE focuses on building a cohesive european SDV ecosystem by coordinating stakeholders such as OEMs, tiers, semiconductor companies, and research institutions. It supports the agile development of a non-differentiating automotive software platform through open-source collaboration, fostering a vibrant SDV community and providing guidance for ongoing and future SDV projects. Meanwhile, HAL4SDV aligns with the ECS Strategic Research and Innovation Agenda to develop technologies and processes needed for SDV advancement beyond 2030. HAL4SDV's objectives include creating a unified software interface, hardware abstraction, and Over-The-Air updates, while focusing on cybersecurity, real-time capabilities, and seamless integration of new software functions and modified software building blocks into the target vehicle system. Together, these projects aim to drive innovation, scalability, and sustainability in the SDV area.

关键词： Industries Technological innovation Scalability Ecosystems europe Focusing Software Real-time systems Hardware Automotive engineering

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Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing

Exploring Large Integer Multiplication for Cryptography Targ...

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design, automation and test in europe conference and exhibition

作者： Florian Krieger Florian Hirner Sujoy Sinha Roy Graz University of Technology Graz Austria

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Emerging cryptographic systems such as Fully Homomorphic Encryption (FHE) and Zero-Knowledge Proofs (ZKP) are computation- and data-intensive. FHE and ZKP implementations in software and hardware largely rely on the von Neumann architecture, where a significant amount of energy is lost on data movements. A promising computing paradigm is computing in memory (CIM) which enables computations to occur directly within memory thereby reducing data movements and energy consumption. However, efficiently performing large integer multiplications - critical in FHE and ZKP - is an open question, as existing CIM methods are limited to small operand sizes. In this work, we address this question by exploring advanced algorithmic approaches for large integer multiplication, identifying the Karatsuba algorithm as the most effective for CIM applications. Thereafter, we design the first Karatsuba multiplier for resistive CIM crossbars. Our multiplier uses a three-stage pipeline to enhance throughput and, additionally, balances memory endurance with efficient array sizes. Compared to existing CIM multiplication methods, when scaled up to the bit widths required in ZKP and FHE, our design achieves up to 916x in throughput and 281x in area-time product improvements.

关键词： Energy consumption Pipelines europe Throughput In-memory computing Common Information Model (computing) Software Hardware Cryptography Homomorphic encryption

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Exact Schedulability Analysis for Limited-Preemptive Parallel Applications Using Timed Automata in UPPAAL

Exact Schedulability Analysis for Limited-Preemptive Paralle...

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design, automation and test in europe conference and exhibition

作者： Jonas Hansen Srinidhi Srinivasan Geoffrey Nelissen Kim G. Larsen DEIS Aalborg Universitet Aalborg Denmark IRIS Eindhoven University of Technology Eindhoven The Netherlands

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

We study the problem of verifying schedulability and ascertaining response time bounds of limited-preemptive parallel applications with uncertainty, scheduled on multi-core platforms. While sufficient techniques exist for analysing schedulability and response time of parallel applications under fixed-priority scheduling, their accuracy remains uncertain due to the lack of a scalable and exact analysis that can serve as a ground-truth to measure the pessimism of existing sufficient analyses. In this paper, we address this gap using formal methods. We use Timed Automata and the powerful UPPAAL verification engine to develop a generic approach to model parallel applications and provide a scalable and exact schedulability and response time analysis. This work establishes a benchmark for evaluating the accuracy of both existing and future sufficient analysis techniques. Furthermore, our solution is easily extendable to more complex task models thanks to its flexible model architecture.

关键词： Adaptation models Accuracy Uncertainty Measurement uncertainty Automata europe Benchmark testing Parallel processing Time measurement Time factors

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