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共 1494 条记录，以下是151-160 订阅

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Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0)

Multi-Partner Project: Artificial Intelligence in Manufactur...

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design, automation and test in europe conference and exhibition

作者： Anouar Nechi Yasin Ghafourian Belal Abu Naim Thomas Gutt George Dimitrakopoulos Amira Moualhi Mladen Berekovic Pal Varga Markus Tauber University of Lübeck * Lübeck Germany Research Studios Austria * Vienna Austria IFAG BEX RDE RDF CFA Infineon Technologies AG * Neubiberg Germany Harokopio University Athens Greece Budapest University of Technology and Economics * Budapest Hungary

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The industrial landscape is undergoing a transformative shift towards Industry 5.0, a paradigm characterized by the convergence of sustainability, digital autonomy, and human-centric design. This article focuses on the adoption, enhancement, and implementation of AI-driven hardware, tools, methodologies, and semiconductor technologies in this progression. We present here a comprehensive strategy from the AIMS5.0 project with the objective of connecting academic developments with practical industrial use, fostering a harmonious relationship between humans and machines to improve efficiency, spur innovation, and enhance adaptability. Hence we show here our global vision, and examples of how the creation of AI-based industrial solutions is supported by novel AI-tool chains, advancements in hardware, and tools supporting human aspects.

关键词： Technological innovation europe Cyber-physical systems Hardware Manufacturing Sustainable development Artificial intelligence Fifth Industrial Revolution Optimization Convergence

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Efficient SAT-Based Bounded Model Checking of Evolving Systems

Efficient SAT-Based Bounded Model Checking of Evolving Syste...

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design, automation and test in europe conference and exhibition

作者： Sophie Andrews Matthew Sotoudeh Clark Barrett Stanford University

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

SAT-based verification is a common technique used by industry practitioners to find bugs in computer systems. However, these systems are rarely designed in a single step: instead, designers repeatedly make small modifications, reverifying after each change. With current tools, this reverification step takes as long as a full, from-scratch verification, even if the design has only been modified slightly. We propose a novel SAT-based verification technique that performs significantly better than the naïve approach in the setting of evolving systems. The key idea is to reuse information learned during the verification of earlier versions of the system to speed up the verification of later versions. We instantiate our technique in a bounded model checking tool for SystemVerilog code and apply it to a new benchmark set based on real edit history for a set of open source RISC-V cores. This new benchmark set is now publicly available for further research on verification of evolving systems. Our tool, PrediCore, significantly improves the time required to verify properties on later versions of the cores compared to the current state-of-the-art, verify-from-scratch approach.

关键词： Industries Software algorithms Computer bugs europe Model checking Benchmark testing Prediction algorithms Hardware Software History

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Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-Skipping

Thanos: Energy-Efficient Keyword Spotting Processor with Hyb...

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design, automation and test in europe conference and exhibition

作者： Sangyeon Kim Hyunmin Kim Sungju Ryu Department of Electronic Engineering Sogang University Seoul Republic of Korea Department of System Semiconductor Engineering Sogang University Seoul Republic of Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In recent years, the keyword spotting algorithm has gained significant attention for applications such as personalized virtual assistants. However, the keyword spotting system must be always turned on to listen to the input voice for the recognition, which worsens the battery constraint problem in the edge devices. In this paper, we first analyze the sparsities in the keyword spotting computation. Based on the characteristic, we introduce the keyword spotting processor called Thanos to enable the zero-skipping scheme in the multiple keyword spotting domains to mitigate the burdensome energy consumption. Experimental results show that our hybrid-domain zero-skipping scheme reduces the latency by 80.3-87.3% and energy consumption by 48.1-79.8% on average, respectively, over the baseline architecture.

关键词： Energy consumption Virtual assistants europe Computer architecture Speech recognition CMOS technology Energy efficiency Batteries Low latency communication Hardware acceleration

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Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention

Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Tempo...

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design, automation and test in europe conference and exhibition

作者： Bangqi Fu Lixin Liu Qijing Wang Yutao Wang Martin D.F. Wong Evangeline F.Y. Young Department of Computer Science and Engineering The Chinese University of Hong Kong

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The analysis of IR-drop stands as a fundamental step in optimizing the power distribution network (PDN), and subsequently influences the design performance. However, traditional IR-drop analysis using commercial tools proves to be exceedingly time-consuming. Fast and accurate IR-drop analysis is desperately in demand to achieve high performance on timing and power. Recently, machine learning approaches have garnered attention owing to their remarkable speed and extensibility in IC designs. However, prior works for dynamic IR-drop prediction presented limited performance since they did not exploit the time-varying activities. In this paper, we proposed a dual-path model with spatial-temporal transformers to extract the static spatial features and dynamic time-variant activities for dynamic IR drop prediction. Experimental results on the large-scale advanced dataset CircuitNet show that our model significantly outperforms the state-of-the-art works.

关键词： Runtime europe Machine learning Predictive models Feature extraction Transformers Extensibility Timing Reliability Integrated circuit modeling

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One More Motivation to Use Evaluation Tools This Time for Hardware Multiplicative Masking of AES

One More Motivation to Use Evaluation Tools This Time for Ha...

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design, automation and test in europe conference and exhibition

作者： Hemin Rahimi Amir Moradi Technische Universität Darmstadt Darmstadt Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Safeguarding cryptographic implementations against the increasing threat of Side-Channel Analysis (SCA) attacks is essential. Masking, a countermeasure that randomizes intermediate values, is a cornerstone of such defenses. In particular, SCA-secure implementation of AES, the most-widely used encryption standard, can employ Boolean masking as well as multiplicative masking due to its underlying Galois field operations. However, multiplicative masking is susceptible to vulnerabilities, including the zero-value problem, which has been identified right after the introduction of multiplicative masking. At CHES 2018, De Meyer et al. proposed a hardware-based approach to manage these challenges and implemented multiplicative masking for AES, incorporating a Kronecker delta function and randomness optimization. In this work, we evaluate their design using the PROLEAD evaluation tool under the glitch-and transition-extended probing model. Our findings reveal a critical vulnerability in their first-order implementation of the Kronecker delta function, stemming from the employed randomness optimization. This leakage com-promises the security of their presented masked AES Sbox. After pinpointing the source of such a leakage, we propose an alternative randomness optimization to address this issue, and demonstrate its effectiveness through rigorous evaluations by means of PROLEAD.

关键词： Silver Focusing europe Hardware Encryption Galois fields Optimization Standards Formal verification

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Efficient Approximate Logic Synthesis with Dual-Phase Iterative Framework

Efficient Approximate Logic Synthesis with Dual-Phase Iterat...

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design, automation and test in europe conference and exhibition

作者： Ruicheng Dai Xuan Wang Wenhui Liang Xiaolong Shen Menghui Xu Leibin Ni Gezi Li Weikang Qian UM-SJTU Joint Inst. Huawei Tech. Co. Ltd. China MoE Key Lab of AI Shanghai Jiao Tong University China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Approximate computing is an emerging paradigm to improve the energy efficiency for error-tolerant applications. Many iterative approximate logic synthesis (ALS) methods were proposed to automatically design approximate circuits. However, as the sizes of circuits grow, the runtime of ALS grows rapidly. Thus, a crucial challenge is to ensure circuit quality while improving the efficiency of ALS. This work proposes a dual-phase iterative framework to accelerate the iterative ALS flows. In the first phase, a comprehensive circuit analysis is performed to gather the necessary information, including the error information. In the second phase, minimal incremental computation is employed based on the information from the first phase. The experimental results show that the proposed method achieves an acceleration by up to 21.8 × without loss of circuit quality compared to the state-of-the-art methods.

关键词： Runtime Error analysis Approximate computing europe Energy efficiency Circuit synthesis Iterative methods Logic Circuit analysis

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RTHeter: Simulating Real-Time Scheduling of Multiple Tasks on Heterogeneous Architectures

RTHeter: Simulating Real-Time Scheduling of Multiple Tasks o...

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design, automation and test in europe conference and exhibition

作者： Yinchen Ni Jiace Zhu Yier Jin An Zou Shanghai Jiao Tong University University of Florida

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The rising popularity of AI applications is driving the adoption of heterogeneous computing architectures to handle complex computations. However, as these heterogeneous architectures grow more complex, optimizing the scheduling of multiple tasks and meeting strict timing constraints becomes significantly challenging. Current studies on real-time scheduling on heterogeneous processors lack agile and flexible simulation tools that can quickly adapt to varying system settings, leading to inefficiencies in system design. Additionally, the high costs associated with evaluating real-time performance in terms of human and facility efforts further complicate the development process. To address these challenges, this paper introduces a comprehensive hierarchical simulating approach and a corresponding simulator designed for flexible heterogeneous computing platforms. The simulator supports ideal or practical, off-the-shelf or customizable heterogeneous architectures, upon which the simulator can execute both parallel and dependent tasks. Utilizing this simulator, we present two case studies that were time-consuming previously but are now easily achieved by the proposed simulator. The first case study reveals the possibility of using policy-based reinforcement learning to explore novel scheduling strategies; the second explores the dominant processors within heterogeneous architectures, providing insights for optimizing the heterogeneous architecture design.

关键词： Program processors Costs Processor scheduling europe Computer architecture Reinforcement learning Real-time systems Heterogeneous networks Timing System analysis and design

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Multi-Partner Project: LoLiPoP-IoT – design and Simulation of Energy-Efficient Devices for the Internet of Things

Multi-Partner Project: LoLiPoP-IoT – Design and Simulation ...

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design, automation and test in europe conference and exhibition

作者： Jakub Lojda Josef Strnadel Pavel Smrz Vaclav Simek Faculty of Information Technology IT4Innovations Centre of Excellence Brno University of Technology Brno Czech Republic

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper presents an overview of the Internet of Things (IoT) device design and simulation, with a specific focus on low-power design principles - everything in the context of the LoLiPoP-IoT project. The project aims to enhance IoT device usability by reducing maintenance requirements related to battery recharging or replacement. Another key goal is to significantly decrease the massive waste generated by discarded primary batteries, contributing to more sustainable and user-friendly IoT solutions for the future. The primary focus of this paper is on a custom IoT localization tag, for which we simulate solar cells - ranging from basic modeling to their integration into electrical circuits - and the power consumption of the tag's electronics platform. The analyzed sample platform is built on the nRF52833 microcontroller and the DW3110 ultra-wideband transceiver. We also applied our experimental framework principles to optimize power consumption and extend battery life. Reductions in photovoltaic panel area were achieved for both devices with a 5-year lifespan and fully autonomous tags, though with increased localization latency. Furthermore, this paper demonstrates how IoT devices, including their firmware, can be effectively modeled and simulated using publicly available tools.

关键词： Location awareness Power demand Photovoltaic cells Circuits europe Energy efficiency Batteries Internet of Things Usability Microprogramming

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Transistor Aging and Circuit Reliability at Cryogenic Temperatures

Transistor Aging and Circuit Reliability at Cryogenic Temper...

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design, automation and test in europe conference and exhibition

作者： Javier Diaz-Fortuny Vishal Nayar Advanced Reliability Robustness and Test imec Leuven Belgium

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The increasing interest in cryogenic circuits is driven by their transformative potential across high-performance computing, medical devices, space exploration, and quantum technologies. Operating transistors at cryogenic temperatures, such as 77 K and below, yields substantial improvements, including increased ON current, reduced OFF current, and enhanced sub-threshold slope. While recent studies have explored device-level reliability at cryogenic temperatures, circuit-level reliability-particularly under bias temperature instability (BTI)-remains underexamined, leaving critical aging mechanisms at these temperatures not well understood. To bridge this gap, we designed and fabricated a customized chip in a commercial HKMG 28 nm technology. The chip integrates several ring oscillator (RO) circuits for precise characterization of accelerated aging effects, enabling evaluation of their impact on performance at cryogenic temperatures. Finally, we project technology degradation in a 10-year future comparing, the achieved wear out between room temperature (298 K) and at 77 K when operating circuits at the nominal voltage, revealing the significant mitigation of BTI aging when operating at affordable cryogenic temperatures.

关键词： Degradation Ring oscillators Semiconductor device measurement Voltage measurement Cooling Accelerated aging Liquid nitrogen Space exploration Transistors Integrated circuit reliability

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Are LLMs Ready for Practical Adoption for Assertion Generation?

Are LLMs Ready for Practical Adoption for Assertion Generati...

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design, automation and test in europe conference and exhibition

作者： Vaishnavi Pulavarthi Deeksha Nandal Soham Dan Debjit Pal Electrical and Computer Engg. Dept. University of Illinois Chicago Chicago USA Microsoft

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Assertions have been the de facto collateral for simulation-based and formal verification of hardware designs for over a decade. The quality of hardware verification, i.e., detection and diagnosis of corner-case design bugs, is critically dependent on the quality of the assertions. With the onset of generative AI such as Transformers and Large-Language Models (LLMs), there has been a renewed interest in developing novel, effective, and scalable techniques of generating functional and security assertions from design source code. While there have been recent works that use commercial-of-the-shelf (COTS) LLMs for assertion generation, there is no comprehensive study in quantifying the effectiveness of LLMs in generating syntactically and semantically correct assertions. In this paper, we first discuss AssertionBench from our prior work, a comprehensive set of designs and assertions to quantify the goodness of a broad spectrum of COTS LLMs for the task of assertion generations from hardware design source code. Our key insight was that COTS LLMs are not yet ready for prime-time adoption for assertion generation as they generate a considerable fraction of syntactically and semantically incorrect assertions. Motivated by the insight, we propose AssertionLLM, a first of its kind LLM model, specifically fine-tuned for assertion generation. Our initial experimental results show that AssertionLLM considerably improves the semantic and syntactic correctness of the generated assertions over COTS LLMs.

关键词： Generative AI Source coding Semantics Computer bugs europe Syntactics Transformers Hardware Security Formal verification

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