The proceedings contain 301 papers. The topics discussed include: trade offs in the design of a router with both guaranteed and best-effort services for networks on chip;communication centric architectures for turbo-d...
The proceedings contain 301 papers. The topics discussed include: trade offs in the design of a router with both guaranteed and best-effort services for networks on chip;communication centric architectures for turbo-decoding on embedded multiprocessors;packetized on-chip interconnect communication analysis for MPSoC;system level specification in lava;formal semantics of synchronous systemC;systemC-AMS requirements, design objectives and rationale;parallel processing architectures for reconfigurable systems;different approaches to add reconfigurability in a SoC architecture;creating value through test;data space oriented scheduling in embedded systems;an efficient hash table based approach to avoid state space explosion in history driven quasi-static scheduling;and a novel metric for interconnect architecture performance.
The proceedings contain 217 papers. The topics discussed include: dual threshold voltage domino logic synthesis for high performance with noise and power constraint;a fitting approach to generate symbolic expressions ...
The proceedings contain 217 papers. The topics discussed include: dual threshold voltage domino logic synthesis for high performance with noise and power constraint;a fitting approach to generate symbolic expressions for linear and nonlinear analog circuit performance characteristics;parameter controlled automatic symbolic analysis of nonlinear analog circuits;constructing symbolic models for the input/output behavior of periodically time-varying systems using harmonic transfer matrices;Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification;dynamic runtime re-scheduling allowing multiple implementations of a task for platform-based designs;global optimization applied to the oscillator problem;and reducing test application time through test data mutation encoding.
The proceedings contain 378 papers. The topics discussed include: evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP;BlockAMC: scalable...
ISBN:
(纸本)9798350348590
The proceedings contain 378 papers. The topics discussed include: evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP;BlockAMC: scalable in-memory analog matrix computing for solving linear systems;microprocessor design space exploration via space partitioning and Bayesian optimization;an efficient asynchronous circuits design flow with backward delay propagation constraint;ReTAP: processing-in-ReRAM Bitap approximate string matching accelerator for genomic analysis;learning assisted post-manufacture testing and tuning of RRAM-based DNNs for yield recovery;towards cycle-based shuttling for trapped-ion quantum computers;heterogeneous static timing analysis with advanced delay calculator;and decentralized federated learning in partially connected networks with non-IID data.
The proceedings contain 299 papers. The topics discussed include: embedded systems design - scientific challenges and work directions;a low-power fat tree-based optical network-on-chip for multiprocessor system-on-chi...
ISBN:
(纸本)9783981080155
The proceedings contain 299 papers. The topics discussed include: embedded systems design - scientific challenges and work directions;a low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip;SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips;user-centric design space exploration for heterogeneous network-on-chip platforms;a highly resilient routing algorithm for fault-tolerant NoCs;mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture;an ILP formulation for task mapping and scheduling on multi-core architectures;DPR in high energy physics;a flexible layered architecture for accurate digital baseband algorithm development and verification;lifetime reliability-aware task allocation and scheduling for MPSoC platforms;integrated scheduling and synthesis of control applications on distributed embedded systems;and pipelined data parallel task mapping/scheduling technique for MPSoC.
The proceedings contain 143 papers. The topics discussed include: modeling electromagnetic emission of integrated circuits for system analysis;analysis of EME produced by a microcontroller operations;minimizing stand-...
The proceedings contain 143 papers. The topics discussed include: modeling electromagnetic emission of integrated circuits for system analysis;analysis of EME produced by a microcontroller operations;minimizing stand-by leakage power in static CMOS circuits;in-place delay constrained power optimization using functional symmetries;high-quality sub-function construction in functional decomposition based on information relationship measures;generalized reasoning scheme for redundancy addition and removal logic optimization;LPSAT: a unified approach to RTL satisfiability;high quality behavioral verification using statistical stopping criteria;efficient inductance extraction via windowing;and explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.
The proceedings contain 140 papers. The topics discussed include: exploiting state equivalence on the fly while applying code motion and speculation;single chip or hybrid system integration;testing the configurable in...
The proceedings contain 140 papers. The topics discussed include: exploiting state equivalence on the fly while applying code motion and speculation;single chip or hybrid system integration;testing the configurable interconnect/logic interface of SRAM-based FPGA's;industrial evaluation of DRAM tests;industrial evaluation of DRAM tests;ATPG tools for delay faults at the functional level;performance driven resynthesis by exploiting retiming-induced state register equivalence;minimizing sensitivity to delay variations in high-performance synchronous circuits;retiming sequential circuits with multiple register classes;chip-level verification for parasitic coupling effects in deep-submicron digital designs;and coupled noise estimation for distributed RC interconnect model.
The proceedings contain 138 papers. The topics discussed include: transformational placement and synthesis;power and delay reduction via simultaneous logic and placement optimization in FPGAs;constructive library-awar...
The proceedings contain 138 papers. The topics discussed include: transformational placement and synthesis;power and delay reduction via simultaneous logic and placement optimization in FPGAs;constructive library-aware synthesis using symmetries;a BIST scheme for on-chip ADC and DAC testing;an on chip ADC test structure;reuse of existing resources for analog BIST of a switch capacitor filter;a BDD-based satisfiability infrastructure using the unate recursive paradigm;automatic lighthouse generation for directed state space search;analyzing real-time systems;a generic architecture for on-chip packet-switched interconnections;memory arbitration and cache management in stream-based systems;HW/SW Codesign of an engine management system;wave steered FSMs;and gate sizing using a statistical delay model.
The proceedings contain 286 papers. The topics discussed include: on ESL verification of memory consistency for system-on-chip multiprocessing;a clustering-based scheme for concurrent trace in debugging NoC-based mult...
ISBN:
(纸本)9783981080186
The proceedings contain 286 papers. The topics discussed include: on ESL verification of memory consistency for system-on-chip multiprocessing;a clustering-based scheme for concurrent trace in debugging NoC-based multicore systems;dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design;DRAM selection and configuration for real-time mobile systems;smart power unit with ultra low power radio trigger capabilities for wireless sensor networks;off-path leakage power aware routing for SRAM-based FPGAs;a divide and conquer based distributed run-time mapping methodology for many-core platforms;EDA solutions to new-defect detection in advanced process technologies;accurately timed transaction level models for virtual prototyping at high abstraction level;SURF algorithm in FPGA: a novel architecture for high demanding industrial applications;and benefits of green energy and proportionality in high speed wide area networks connecting data centers.
The proceedings contain 311 papers. The topics discussed include: moDNN: memory optimal DNN training on GPUs;MATIC: learning around errors for efficient low-voltage neural network accelerators;efficient verification o...
ISBN:
(纸本)9783981926316
The proceedings contain 311 papers. The topics discussed include: moDNN: memory optimal DNN training on GPUs;MATIC: learning around errors for efficient low-voltage neural network accelerators;efficient verification of multi-property designs (the benefit of wrong assumptions);symbolic quick error detection using symbolic initial state for pre-silicon verification;HVSM: hardware-variability aware streaming processors' management policy in GPUs;throughput optimization and resource allocation on GPUs under multi-application execution;set variation-aware shared LLC management for CPU-GPU heterogeneous architecture;cyclic locking and memristor-based obfuscation against CyCSAT and inside foundry attacks;TimingCamouflage: improving circuit security against counterfeiting by unconventional timing;advancing hardware security using polymorphic and stochastic spin-hall effect devices;main memory organization trade-offs with dram and STT-MRAM options based on gem5-nvmain simulation frameworks;exploring the opportunity of implementing neuromorphic computing systems with spintronic devices;novel application of spintronics in computing, sensing, storage and cybersecurity;the FED4SAE project, accelerating european cps solutions to market;and transferring research results to safety-relevant products: case study on automated driving software.
The proceedings contain 312 papers. The topics discussed include: VESPA: variability emulation for system-on-chip performance analysis;thermal-aware on-line task allocation for 3D multi-core processor throughput optim...
ISBN:
(纸本)9783981080179
The proceedings contain 312 papers. The topics discussed include: VESPA: variability emulation for system-on-chip performance analysis;thermal-aware on-line task allocation for 3D multi-core processor throughput optimization;an endurance-enhanced flash translation layer via reuse for NAND flash memory storage systems;fast statistical analysis of RC nets subject to manufacturing variabilities;a block-diagonal structured model reduction scheme for power grid networks;parallel accelerators for GlimmerHMM bioinformatics algorithm;an efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms;sub-clock power-gating technique for minimizing leakage power during active mode;an automated data structure migration concept - from CAN to Ethernet/IP in automotive embedded systems (CANoverIP);and formal specification and systematic model-driven testing of embedded automotive systems.
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