The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficie...
The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficient identification of testable path delay faults;Z-sets and Z-detections: circuit characteristics that simplify fault diagnosis;loop shifting and compaction for the high-level synthesis of designs with complex control flow;re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus;a mapping strategy for resource-efficient network processing on multiprocessor SoCs;design of sub-10-picoseconds on-chip time measurement circuit;automated, accurate macromodelling of digital aggressors for power/ground/substrate noise prediction;a high-speed transceiver architecture implementable as synthesizable IP core;and verification of a microcontroller IP core for system-on-a-chip designs using low-cost prototyping environments.
The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficie...
ISBN:
(纸本)0769520855
The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficient identification of testable path delay faults;Z-sets and Z-detections: circuit characteristics that simplify fault diagnosis;loop shifting and compaction for the high-level synthesis of designs with complex control flow;re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus;a mapping strategy for resource-efficient network processing on multiprocessor SoCs;design of sub-10-picoseconds on-chip time measurement circuit;automated, accurate macromodelling of digital aggressors for power/ground/substrate noise prediction;a high-speed transceiver architecture implementable as synthesizable IP core;and verification of a microcontroller IP core for system-on-a-chip designs using low-cost prototyping environments.
The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficie...
ISBN:
(纸本)0769520855
The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficient identification of testable path delay faults;Z-sets and Z-detections: circuit characteristics that simplify fault diagnosis;loop shifting and compaction for the high-level synthesis of designs with complex control flow;re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus;a mapping strategy for resource-efficient network processing on multiprocessor SoCs;design of sub-10-picoseconds on-chip time measurement circuit;automated, accurate macromodelling of digital aggressors for power/ground/substrate noise prediction;a high-speed transceiver architecture implementable as synthesizable IP core;and verification of a microcontroller IP core for system-on-a-chip designs using low-cost prototyping environments.
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