In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We...
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ISBN:
(纸本)0769522882
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.
This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this concept for ATPG for diagnosing faults...
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ISBN:
(纸本)0769522882
This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this concept for ATPG for diagnosing faults on analog networks. Such method relies on evolutionary techniques, where a generic algorithm (GA) is coded to generate a set of optimum frequencies capable to disclose faults.
At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manufacturing. However, at-speed fault coverage and test-efficacy suffer when tests are not robust. Since Automa...
ISBN:
(纸本)9783981080186
At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manufacturing. However, at-speed fault coverage and test-efficacy suffer when tests are not robust. Since Automatic test Pattern Generation (ATPG) is typically performed at late design stages, fixing robustness problems found during ATPG can be costly. To address this challenge, we propose a methodology that identifies robustness problems at the Register Transfer Level (RTL) and fixes them. Empirically, this improves final at-speed fault coverage and test-efficacy.
This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. S...
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ISBN:
(纸本)0769522882
This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products;i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 um technology. IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this methodology obviously reduces the routi...
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ISBN:
(纸本)9783981080131
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this methodology obviously reduces the routing cost when compared to the case that dedicated test buses are introduced as TAMs, it is not clear whether it is beneficial in terms of other important factors that significantly affect test cost, e.g., testing time, test control complexity and test reliability. As a result, in this paper we re-examine the issue of using NoC as TAM in order to facilitate designers to construct a cost-effective system test architecture based on their requirements(1).
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and model...
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ISBN:
(纸本)9783981080124
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains. Industry-level AEMS integration, and more prospective microfluidic biochip systems are considered at both technological and EDA levels. Final v, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed.
Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a system-on-chip (SoC) i...
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ISBN:
(纸本)9783981080131
Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test This power variation adversely affects predictions of temperature and the time required for burn-in. We present a test-scheduling technique for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Simulation results are presented for two ITC'02 SoC benchmarks, and the proposed technique is compared with two baseline methods.
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper we present a novel scan design methodology to maximize di...
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ISBN:
(纸本)9783981080131
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay, tes...
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ISBN:
(纸本)9783981080124
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay, test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay fault coverage is usually attributed to the fact that two-pattern test foil delay, testing cannot be delivered to modules under test in consecutive cycles. To solve the problem, we propose an HLTS method that ensures valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in functional units, while the fault covet-age in circuits synthesized by LEA-based allocation algorithm is rather poor. The area overhead due to this method ranges from 2% to 10% for 16-bit datapaths.
This paper presents a novel VLSI implementation of a MIMO detector for OFDM systems. The proposed architecture is able to perform both linear MMSE and reduced latticeaided MIMO detection, making it possible to adjust ...
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ISBN:
(纸本)9781424437818
This paper presents a novel VLSI implementation of a MIMO detector for OFDM systems. The proposed architecture is able to perform both linear MMSE and reduced latticeaided MIMO detection, making it possible to adjust the balance between performance and power consumption. In order to facilitate real-time detection in reduced lattice mode of operation, a novel fixed-complexity version of the LLL lattice reduction algorithm has been developed, allowing for strict practical timing requirements, such as those specified for new generation IEEE 802.11n wireless LAN systems, to be met. An implementation of the MIMO detector for a system employing up to 4 transmit and receive antennas is described and its complexity and performance are evaluated.
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