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design, modeling, and simulation in microelectronics

This Volume 4228 of the conference proceedings contains 45 papers. Topics discussed include computer aided design for microelectronics and microelectromechanical devices, advanced design method, high level synthesis a... 详细信息

关键词： microelectronics

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microelectronics Package design Using Experimentally-Validated modeling and simulation

Microelectronics Package Design Using Experimentally-Validat...

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4th International Symposium on Advanced Ceramics (ISAC-4)

作者： Young, Nathan Johnson, Jay Ewsuk, Kevin Sandia Natl Labs Albuquerque NM 87185 USA

ISBN: (纸本)9783037851814

Packaging high power radio frequency integrated circuits (RFICs) in low temperature cofired ceramic (LTCC) presents many challenges. Within the constraints of LTCC fabrication, the design must provide the usual electrical isolation and interconnections required to package the IC, with additional consideration given to RF isolation and thermal management. While iterative design and prototyping is an option for developing RFIC packaging, it would be expensive and most likely unsuccessful due to the complexity of the problem. To facilitate and optimize package design, thermal and mechanical simulations were used to understand and control the critical parameters in LTCC package design. The models were validated through comparisons to experimental results. This paper summarizes an experimentally-validated modeling approach to RFIC package design, and presents some results and key findings.

关键词： microelectronics Thermal Management LTCC Packaging RFIC

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SMACD / PRIME 2021 - International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design and 16th Conference on PhD Research in microelectronics and Electronics

SMACD / PRIME 2021 - International Conference on Synthesis, ...

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2021 International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th Conference on PhD Research in microelectronics and Electronics, PRIME 2021

ISBN: (纸本)9783800755899

The proceedings contain 99 papers. The topics discussed include: run-time adaptive hardware accelerator for convolutional neural networks;design and analysis of a leading one detector-based approximate multiplier on FPGA;extending a RISC-V core with an AES hardware accelerator to meet IOT constraints;memristive logic-in-memory implementations: a comparison;a low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process;A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application;implementation of a low power decimation filter in a 180 nm HV-CMOS technology for a neural recording front-end;and analog baseband filter and variable-gain amplifier for automotive radars in 22 nm FD-SOI CMOS.

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Transfer Learning Framework for 3-D Electromagnetic Applications

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2025年

作者： Akinwande, Oluwaseyi Jia, Xiaofan Deroo, Andries Lu, Yang Lin, Hank Tseng, Bin-Chyi Swaminathan, Madhavan Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA ASUS Taipei 112 Taiwan Penn State Univ Sch Elect Engn & Comp Sci State Coll PA 16802 USA

In the realm of machine-learning (ML)-based electronic design automation (EDA), several factors contribute to inefficiency, posing various challenges. Initially, the lack of flexibility in input structures hinders the sharing of information across different circuit topologies. In addition, substantial costs are incurred in terms of simulation run times during the data generation process due to the necessity of creating a large training dataset for each circuit topology. To this effect, in this article, we address the dual problem of how to: 1) develop a general unified surrogate model that can handle a variety of circuit topologies and 2) employ previously trained models and adapt them to new models. We provide a formulation for transforming 3-D electromagnetic (EM) circuits into versatile circuit graphs, for a variety of topologies, imbued with structural information. The absence of such frameworks represents a gap in ML-based EDA, which we fill by providing a set of building blocks to achieve significant improvements in modeling tasks. Finally, we present a versatile forward modeling framework that allows one to quickly obtain the output response given a set of design parameters. We achieve the overarching goal of reducing the resources needed to create an ML model library for signal integrity (SI) applications in microelectronics packaging.

关键词： Integrated circuit modeling Topology Transfer learning Training Packaging microelectronics Circuit topology Microwave circuits Couplings Transmission line matrix methods Electromagnetic (EM) modeling graph neural network (GNN) high-speed channels semiconductor packaging signal integrity (SI) surrogate modeling transfer learning

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Warpage prediction of fan-out wafer-level package based on coupled deep learning and finite element simulation

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microelectronics RELIABILITY 2025年 170卷

作者： Zhao, Xiaohui Zheng, Hao Zhao, Zhiyan Cheng, Mengxuan Li, Wenqian Wan, Guoshun Jia, Yuxi Shandong Univ Sch Mat Sci & Engn 17923Jingshi Rd Jinan 250061 Shandong Peoples R China Shandong Univ Sci & Technol Coll Comp Sci & Engn 579Qianwangang Rd Qingdao 266590 Shandong Peoples R China

In recent years, fan-out wafer-level package (FOWLP) has gained widespread attention in integrated circuit industry due to its significant potential in enhancing packaging performance, reducing costs and minimizing size. However, accurate prediction of warpage in FOWLP remains a formidable challenge, as conventional prediction methods often suffer from prolonged iterative cycles and high computational costs. This study integrates the finite element method (FEM) with artificial intelligence (AI) techniques to develop highly accurate and efficient warpage prediction model for FOWLP based on varying chip sizes and spacings. Automated modeling and data generation were performed using simulation technique and python scripts, resulting in the creation of two datasets of different scales for regression training and optimization. Prediction results indicate that Residual Network-152 (ResNet-152) performs best on smaller datasets, while Global Context Vision Transformer-Tiny (GCViT-Tiny) exhibits greater stability on larger datasets. The Huber loss function was employed to optimize the deep learning (DL) model weights through backpropagation, significantly improving both training efficiency and prediction accuracy. Additionally, the reliability and practicality of the DL model were validated by performing simulations and AI predictions on structures not included in the dataset. Finally, the trained DL model provided brief technical guidance for optimizing warpage in wafers for the integrated circuit industry. In terms of efficiency, DL models offer a clear advantage in industrial applications. The research results provide effective theoretical support and practical guidance for FOWLP optimum design and reliability assessment, demonstrating significant application potential.

关键词： Fan-out wafer-level package (FOWLP) Warpage Artificial intelligence (AI) Deep learning (DL) models Finite element simulation

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modeling and simulation of an All-Digital Pll for Bluetooth Low Energy in Python 16

Modeling and Simulation of an All-Digital Pll for Bluetooth ...

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16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025

作者： Weschenfelder, Anderson Felipe Da Silva Franca, Thiago Rieck, Lucas Gasparin Ferreira, Sandro Binsfeld Polytechnical School Unisinos University São Leopoldo Brazil

ISBN: (纸本)9798331522124

This paper presents the design and modeling of a Bluetooth Low Energy (BLE) All-Digital Phase-Locked Loop (ADPLL) for 28nm CMOS technology. A behavioral model was developed and implemented using event-driven simulation technique to validate the ADPLL specifications. To anticipate process variations on DCO and TDC components, a new method is introduced to integrate inaccuracies into the model, improving the behavioral model realism. The model was designed using Python language targeting in-band phase noise of - 95 dBc / Hz and -108 dBc / Hz at 1 MHz, meeting BLE target requirements. © 2025 IEEE.

关键词： CMOS integrated circuits

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modeling and simulation of plasma etching reactors for microelectronics

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THIN SOLID FILMS 2000年第2期365卷 348-367页

作者： Economou, DJ Univ Houston Dept Chem Engn Plasma Proc Lab Houston TX 77204 USA

As microelectronic devices continue to shrink and process requirements become ever more stringent, plasma modeling and simulation becomes increasingly more attractive as a tool for design, control, and optimization of plasma reactors. A brief introduction and overview of the plasma reactor modeling and simulation problem is presented in this paper. The problem is broken down into smaller pieces (reactor, sheath. microfeature. and crystal lattice) to address the disparity in length scales. A modular approach also helps to resolve the issue of disparity in time scales. (C) 2000 Elsevier Science S.A. All rights reserved.

关键词： plasma etching reactor plasma modeling plasma simulation

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TCAD simulation of Radiation Effects on 180 nm Logic Inverters

TCAD Simulation of Radiation Effects on 180 nm Logic Inverte...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Eike Trumann Amen Allah Bahri Gia Bao Thieu Kirsten Weide-Zaage Dorian Von Wolff Andre Bausen Alexander Müller Guillermo Payá-Vayá Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Braunschweig Germany RESRI Group Institute of Microelectronic Systems (IMS) Leibniz Universität Hannover Hannover Germany Bundeswehr Research Institute for Protective Technologies and CBRN Protection (WIS) Munster Germany

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

This work presents a physically based simulation evaluation of the effects of single ionizing particles and displacement damage on logic inverter gates in a complementary metal-oxide semiconductor (CMOS) with 180 nm structure size. A technology computer-aided-design (TCAD) model is combined with a radiation model to allow the simulation of charged particles with a linear energy transfer (LET) between 1 and 100 $\frac{M e V \cdot c m^simulation}{m g}$ . For displacement damage simulation, proton energies between 1 and 10 MeV and neutron energies between 1.6 and 14 MeV have been evaluated to estimate the resulting transistor threshold voltages.

关键词： Semiconductor device modeling Protons Micromechanical devices Neutrons Pulse inverters Threshold voltage microelectronics Transistors Periodic structures MOS devices

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modeling of FE Parasitic Inductance in BCD Power Switches

Modeling of FE Parasitic Inductance in BCD Power Switches

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Ștefan Ardeleanu Ioan Marius Purcar Cristian Boianceanu Electrotechnics and Measurements Department Technical University of Cluj-Napoca Cluj-Napoca Romania Design Enabling Services Infineon Technologies Romania Bucharest Romania

This paper proposes a calculation methodology for assessing the parasitic inductance within an IC package. As a case study, the BCD technology of one of the top IC suppliers was used. The results will be evaluated aga... 详细信息

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

关键词： Micromechanical devices Inductance Metallization Conductors Reliability engineering Software Finite element analysis microelectronics Transistors Optimization

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Mixed-Level modeling Methodology for Network-on-Chip Architecture Exploration

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Chinese Journal of Electronics 2025年第3期23卷 468-473页

作者： Shouyi Yin Zhen Zhang Yang Hu Leibo Liu Shaojun Wei Institute of Microelectronics Tsinghua University Beijing China National Laboratory for Information Science and Technology Tsinghua University Beijing China

As Network on chip (NoC) architecture de-velops as an solution of interconnection in System on chip (SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation frame-work becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification plat-form. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simu-lation speed, and lower step to relative development of software. The experimental results show that the mixed-level NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.

关键词： Performance evaluation Analytical models Accuracy Multiprocessor interconnection Network-on-chip Software Hardware Space exploration System-level design

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