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SMACD / PRIME 2021 - International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design and 16th Conference on PhD Research in microelectronics and Electronics

SMACD / PRIME 2021 - International Conference on Synthesis, ...

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2021 International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th Conference on PhD Research in microelectronics and Electronics, PRIME 2021

ISBN: (纸本)9783800755899

The proceedings contain 99 papers. The topics discussed include: run-time adaptive hardware accelerator for convolutional neural networks;design and analysis of a leading one detector-based approximate multiplier on FPGA;extending a RISC-V core with an AES hardware accelerator to meet IOT constraints;memristive logic-in-memory implementations: a comparison;a low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process;A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application;implementation of a low power decimation filter in a 180 nm HV-CMOS technology for a neural recording front-end;and analog baseband filter and variable-gain amplifier for automotive radars in 22 nm FD-SOI CMOS.

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2023 24th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems, EuroSimE 2023

2023 24th International Conference on Thermal, Mechanical an...

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24th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems, EuroSimE 2023

ISBN: (纸本)9798350345971

The proceedings contain 105 papers. The topics discussed include: thermomechanical and electrical material characterization for a DLP printing process simulation of electrically conductive parts;studying asymmetric warpage behavior of panel-level packages using process modeling techniques and viscoelasticity theory;using grid search methods and parallel computing to reduce AI training time for reliability lifetime prediction of wafer-level packaging;improved nanoindentation methods for polymer based multilayer film cross-sections;power semiconductor die passivation layer stress mechanism investigation and optimization by numerical analysis;the effect of geometric and material uncertainty on debonding warpage in fan-out panel level packaging;fem simulation of influence of different polymeric module materials and layouts on thermomechanical deformations in strings of shingled solar cells;finite element model for prediction of back-end-of-line process induced wafer bow for patterned wafer;impact of viscoelastic properties on package warpage prediction;influence of the quality of material models on warpage and lifetime prediction by finite element simulation;and design of power modules using containers filled with phase change materials as device top interconnection for power peak management.

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Special Section Guest Editorial: Plasma modeling and Feature Profile simulation

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JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3 2023年第4期22卷

作者： Labelle, Catherine B. Kushner, Mark J. Intel Corp Rio Rancho NM 87124 USA Univ Michigan Ann Arbor MI USA

. Guest Editors Catherine B. Labelle and Mark J. Kushner introduce the Special Section on Plasma modeling and Feature Profile simulation.

关键词： Plasma modeling Computer simulations microelectronics Process modeling Systems modeling design Machine learning Semiconductor manufacturing Vacuum chambers

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Transfer Learning Framework for 3-D Electromagnetic Applications

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2025年

作者： Akinwande, Oluwaseyi Jia, Xiaofan Deroo, Andries Lu, Yang Lin, Hank Tseng, Bin-Chyi Swaminathan, Madhavan Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA ASUS Taipei 112 Taiwan Penn State Univ Sch Elect Engn & Comp Sci State Coll PA 16802 USA

In the realm of machine-learning (ML)-based electronic design automation (EDA), several factors contribute to inefficiency, posing various challenges. Initially, the lack of flexibility in input structures hinders the sharing of information across different circuit topologies. In addition, substantial costs are incurred in terms of simulation run times during the data generation process due to the necessity of creating a large training dataset for each circuit topology. To this effect, in this article, we address the dual problem of how to: 1) develop a general unified surrogate model that can handle a variety of circuit topologies and 2) employ previously trained models and adapt them to new models. We provide a formulation for transforming 3-D electromagnetic (EM) circuits into versatile circuit graphs, for a variety of topologies, imbued with structural information. The absence of such frameworks represents a gap in ML-based EDA, which we fill by providing a set of building blocks to achieve significant improvements in modeling tasks. Finally, we present a versatile forward modeling framework that allows one to quickly obtain the output response given a set of design parameters. We achieve the overarching goal of reducing the resources needed to create an ML model library for signal integrity (SI) applications in microelectronics packaging.

关键词： Integrated circuit modeling Topology Transfer learning Training Packaging microelectronics Circuit topology Microwave circuits Couplings Transmission line matrix methods Electromagnetic (EM) modeling graph neural network (GNN) high-speed channels semiconductor packaging signal integrity (SI) surrogate modeling transfer learning

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PFed-Litho: Lithography modeling with a Personalized Federated Learning Based Framework

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IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems 2024年第6期44卷 2264-2276页

作者： Zhang, Qing Zhang, Yuhang Chen, Rui Lu, Wei Huang, Huajie Li, Zhiqiang Li, Yongfu Shanghai Jiao Tong University Department of Micro-Nano Electronics MoE Key Lab of Artificial Intelligence Shanghai200240 China East China Normal University School of Integrated Circuit Science and Engineering Shanghai200240 China Chinese Academy of Sciences Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Beijing100029 China University of Chinese Academy of Sciences Beijing101408 China

modeling lithography using machine learning is extremely data-intensive. Due to intellectual property privacy concerns and potential malicious attacks, design houses and foundries are unwilling to share their designs directly. To address the aforementioned concerns, we have proposed a personalized federated learning-based framework (pFed-Litho) to perform end-to-end lithography simulation. This framework incorporates a cross-level local training algorithm along with an integrated optimization method to generate personalized and local models, which overcome the generalization problem and slow convergence and oscillatory behavior in its loss function, respectively. The experimental results show that our pFed-Litho framework achieves up to 14.07% higher accuracy with reduced oscillatory behavior in the loss curve compared to the state-of-the-art works. Even with a dataset reduced by 100×, our framework maintains a stable accuracy of over 91%, representing a 50% increase compared to the U-Net model. © 1982-2012 IEEE.

关键词： Lithography Accuracy Computational modeling Training Servers Resists Integrated circuit modeling Data models Complexity theory Federated learning

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modeling, Optimization, and simulation of Nanomaterials-Based Organic Thin Film Transistor for Future Use in pH Sensing

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RECENT PATENTS ON NANOTECHNOLOGY 2024年第1期18卷 45-53页

作者： Moorthy, Vijai Meyyappan Mohan, Viranjay Srivastava Univ KwaZulu Natal Howard Coll Dept Elect Engn ZA-4041 Durban South Africa

Introduction: Applications of Organic Thin Film Transistor (OTFT) range from flexible screens to disposable sensors, making them a prominent research issue in recent decades. A very accurate and exact pH sensing determination, including biosensors, is essential for these ***: In this present research work, authors have proposed a nanomaterial-based OTFT for future pH monitoring and other biosensing applications. This work presents a numerical model of a pH sensor based on Carbon Nano Tubes (CNTs). Sensing in harsh conditions may be possible with the CNTs due to their strong chemical and thermal resilience. This research work describes the numerical modeling of Bottom-Gate Bottom-Contact (BGBC) OTFTs with a Semiconducting Single-Walled Carbon Nanotube (s-SWCNT) and C60 fullerene blended active ***: The design methodology of organic nanomaterial-based OTFTs has been presented with various parameter extraction precisely its electrical characteristics, modeled by adjusting the parameters of the basic semiconductor technology. For an active layer thickness of 200 nm, the drain current of the highest-performing s-SWCNT:C60 -based OTFT structure was around 4.25 A. This demonstrates that it is better than previously reported patents and published ***: This allows for an accurate representation of the device's electrical characteristics. Using Gold (Ag) Source/Drain (S/D) and back-gate electrodes as the medium for sensing, it has been realized how the thickness of the active layer impacts the performance of an OTFT for pH sensor applications.

关键词： High electron mobility transistors (HEMT) hydrogen ion sensor microelectronics nanotechnology organic thin film transistors (OTFT) pH sensors

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A Brief Review of design and simulation Methodology in Silicon Photonics

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Tsinghua Science and Technology 2022年第3期27卷 526-533页

作者： Chonglei Sun Liuge Du Jia Zhao School of Information Science and Engineering Shandong UniversityQingdao 266237China

Powerful electronic design automation tools have enabled the rapid development of electronic Integrated Circuits(ICs). Similar to electronic ICs, silicon photonics technology has sufficiently matured, and large-scale photonic circuits can now be implanted into a single chip. design tools have also evolved from primary devices to complex photonic circuits. In this paper, we review the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic design automation design flows. Key challenges and opportunities are also discussed.

关键词： photonic design automation compact model circuit simulation complex modes

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modeling of HCI effect in nFinFET for circuit reliability simulation

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microelectronics RELIABILITY 2024年 163卷

作者： Zhang, Jun-an Liu, Bo Chen, Hao Li, Chao Li, Dan Li, Tiehu Lu, Yunhua Zhang, Qingwei Chongqing Univ Technol Coll Artificial Intelligence Chongqing Peoples R China

This paper proposes an equivalent circuit model for simulating the Hot Carrier Injection (HCI) effect. This model is developed based on the N-FinFET in the 12 nm Process design Kit (PDK) and incorporates arithmetic units and electrical components from the Electronic design Automatic (EDA) software. Input parameters can be freely modified by the user, such as stress time, ambient temperature, gate length, gate width and process corner. The model also considers the influence of the voltage at each end of the transistor on the HCI effect. The model can be accessed in the EDA tool just like a normal transistor and can be used to evaluate the HCI effect on circuits without modifying the SPICE model. The accuracy and applicability of this model has been verified by comparing it with measured results from other published literature.

关键词： Integrated circuit FinFET Long-term reliability Hot carrier injection effect Aging

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AI-assisted design for Reliability: Review and Perspectives 25

AI-assisted Design for Reliability: Review and Perspectives

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25th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems, EuroSimE 2024

作者： Yuan, Cadmus De Jong, S.D.M. Van Driel, Willem D. Department of Mechanical and Computer-aided Engineering Feng Chia University Taichung Taiwan No. 100 Wenhwa Rd. Seatwen Taichung40724 Taiwan Department of Microelectronics Delft University of Technology Delft Netherlands Mekelweg 4 CD Delft2628 Netherlands

ISBN: (纸本)9798350393637

The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this backdrop, machine learning technologies emerge as dynamic tools for correlation building and classification, revolutionizing the traditional approaches to design, manufacturing, and testing in electronic packaging, as well as the design for Reliability (DfR) *** paper reviews the most recent AI-assisted approach for electronic packaging and then focuses on the AI-assisted DfR (AI-DfR) approaches. Our examination reveals that AI methods have been adapted to meet the specific needs of electronic packaging. The industry's anticipation for AI-DfR stems from its potential to address prevailing reliability design challenges, yet its multidisciplinary essence poses hurdles to swift progress. This review proposes future directions for AI-DfR's development, spotlighting critical areas such as the quality and efficiency of finite element modeling, design and optimization of training models, selection of AI models, and maintenance and value enhancement strategies. © 2024 IEEE.

关键词： AI model design for reliability Electronic Packaging: design Machine learning Manufacturing Testing and Reliability

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modeling and simulation of an All-Digital Pll for Bluetooth Low Energy in Python 16

Modeling and Simulation of an All-Digital Pll for Bluetooth ...

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16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025

作者： Weschenfelder, Anderson Felipe Da Silva Franca, Thiago Rieck, Lucas Gasparin Ferreira, Sandro Binsfeld Polytechnical School Unisinos University São Leopoldo Brazil

ISBN: (纸本)9798331522124

This paper presents the design and modeling of a Bluetooth Low Energy (BLE) All-Digital Phase-Locked Loop (ADPLL) for 28nm CMOS technology. A behavioral model was developed and implemented using event-driven simulation technique to validate the ADPLL specifications. To anticipate process variations on DCO and TDC components, a new method is introduced to integrate inaccuracies into the model, improving the behavioral model realism. The model was designed using Python language targeting in-band phase noise of - 95 dBc / Hz and -108 dBc / Hz at 1 MHz, meeting BLE target requirements. © 2025 IEEE.

关键词： CMOS integrated circuits

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