The proceedings contain 99 papers. The topics discussed include: run-time adaptive hardware accelerator for convolutional neural networks;design and analysis of a leading one detector-based approximate multiplier on F...
ISBN:
(纸本)9783800755899
The proceedings contain 99 papers. The topics discussed include: run-time adaptive hardware accelerator for convolutional neural networks;design and analysis of a leading one detector-based approximate multiplier on FPGA;extending a RISC-V core with an AES hardware accelerator to meet IOT constraints;memristive logic-in-memory implementations: a comparison;a low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process;A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application;implementation of a low power decimation filter in a 180 nm HV-CMOS technology for a neural recording front-end;and analog baseband filter and variable-gain amplifier for automotive radars in 22 nm FD-SOI CMOS.
The proceedings contain 105 papers. The topics discussed include: thermomechanical and electrical material characterization for a DLP printing process simulation of electrically conductive parts;studying asymmetric wa...
ISBN:
(纸本)9798350345971
The proceedings contain 105 papers. The topics discussed include: thermomechanical and electrical material characterization for a DLP printing process simulation of electrically conductive parts;studying asymmetric warpage behavior of panel-level packages using process modeling techniques and viscoelasticity theory;using grid search methods and parallel computing to reduce AI training time for reliability lifetime prediction of wafer-level packaging;improved nanoindentation methods for polymer based multilayer film cross-sections;power semiconductor die passivation layer stress mechanism investigation and optimization by numerical analysis;the effect of geometric and material uncertainty on debonding warpage in fan-out panel level packaging;fem simulation of influence of different polymeric module materials and layouts on thermomechanical deformations in strings of shingled solar cells;finite element model for prediction of back-end-of-line process induced wafer bow for patterned wafer;impact of viscoelastic properties on package warpage prediction;influence of the quality of material models on warpage and lifetime prediction by finite element simulation;and design of power modules using containers filled with phase change materials as device top interconnection for power peak management.
In the realm of machine-learning (ML)-based electronic design automation (EDA), several factors contribute to inefficiency, posing various challenges. Initially, the lack of flexibility in input structures hinders the...
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In the realm of machine-learning (ML)-based electronic design automation (EDA), several factors contribute to inefficiency, posing various challenges. Initially, the lack of flexibility in input structures hinders the sharing of information across different circuit topologies. In addition, substantial costs are incurred in terms of simulation run times during the data generation process due to the necessity of creating a large training dataset for each circuit topology. To this effect, in this article, we address the dual problem of how to: 1) develop a general unified surrogate model that can handle a variety of circuit topologies and 2) employ previously trained models and adapt them to new models. We provide a formulation for transforming 3-D electromagnetic (EM) circuits into versatile circuit graphs, for a variety of topologies, imbued with structural information. The absence of such frameworks represents a gap in ML-based EDA, which we fill by providing a set of building blocks to achieve significant improvements in modeling tasks. Finally, we present a versatile forward modeling framework that allows one to quickly obtain the output response given a set of design parameters. We achieve the overarching goal of reducing the resources needed to create an ML model library for signal integrity (SI) applications in microelectronics packaging.
modeling lithography using machine learning is extremely data-intensive. Due to intellectual property privacy concerns and potential malicious attacks, design houses and foundries are unwilling to share their designs ...
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Introduction: Applications of Organic Thin Film Transistor (OTFT) range from flexible screens to disposable sensors, making them a prominent research issue in recent decades. A very accurate and exact pH sensing deter...
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Introduction: Applications of Organic Thin Film Transistor (OTFT) range from flexible screens to disposable sensors, making them a prominent research issue in recent decades. A very accurate and exact pH sensing determination, including biosensors, is essential for these ***: In this present research work, authors have proposed a nanomaterial-based OTFT for future pH monitoring and other biosensing applications. This work presents a numerical model of a pH sensor based on Carbon Nano Tubes (CNTs). Sensing in harsh conditions may be possible with the CNTs due to their strong chemical and thermal resilience. This research work describes the numerical modeling of Bottom-Gate Bottom-Contact (BGBC) OTFTs with a Semiconducting Single-Walled Carbon Nanotube (s-SWCNT) and C60 fullerene blended active ***: The design methodology of organic nanomaterial-based OTFTs has been presented with various parameter extraction precisely its electrical characteristics, modeled by adjusting the parameters of the basic semiconductor technology. For an active layer thickness of 200 nm, the drain current of the highest-performing s-SWCNT:C60 -based OTFT structure was around 4.25 A. This demonstrates that it is better than previously reported patents and published ***: This allows for an accurate representation of the device's electrical characteristics. Using Gold (Ag) Source/Drain (S/D) and back-gate electrodes as the medium for sensing, it has been realized how the thickness of the active layer impacts the performance of an OTFT for pH sensor applications.
Powerful electronic design automation tools have enabled the rapid development of electronic Integrated Circuits(ICs). Similar to electronic ICs, silicon photonics technology has sufficiently matured, and large-scale ...
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Powerful electronic design automation tools have enabled the rapid development of electronic Integrated Circuits(ICs). Similar to electronic ICs, silicon photonics technology has sufficiently matured, and large-scale photonic circuits can now be implanted into a single chip. design tools have also evolved from primary devices to complex photonic circuits. In this paper, we review the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic design automation design flows. Key challenges and opportunities are also discussed.
This paper proposes an equivalent circuit model for simulating the Hot Carrier Injection (HCI) effect. This model is developed based on the N-FinFET in the 12 nm Process design Kit (PDK) and incorporates arithmetic un...
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This paper proposes an equivalent circuit model for simulating the Hot Carrier Injection (HCI) effect. This model is developed based on the N-FinFET in the 12 nm Process design Kit (PDK) and incorporates arithmetic units and electrical components from the Electronic design Automatic (EDA) software. Input parameters can be freely modified by the user, such as stress time, ambient temperature, gate length, gate width and process corner. The model also considers the influence of the voltage at each end of the transistor on the HCI effect. The model can be accessed in the EDA tool just like a normal transistor and can be used to evaluate the HCI effect on circuits without modifying the SPICE model. The accuracy and applicability of this model has been verified by comparing it with measured results from other published literature.
The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this ...
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As a typical representative technological route of chip technology, microsystems have gradually become one of the main solutions for the small-volume, speciality applications. Heat is the main limitation of the micros...
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