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International Conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yue Zhao Yong Yu Jingrui Guo Lingfei Wang Nan Yang Jianpeng Jiang Yanan Lu Menglong Zhou Shijie Huang Lihua Xu Zhenhua Wu Guanhua Yang Di Geng Guilei Wang Bryan Kang Chao Zhao Ling Li Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Beijing Superstring Academy of Memory Technology Beijing China

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly, fluctuation of disorders in an amorphous channel exhibits a great impact on density of states (DOS) contributing to statistical effects on gate controllability and transport mechanisms. To clarify this issue, TCAD simulations are conducted by adjusting geometric dimensions and DOS, and corresponding statistical characteristics (e.g., on-voltage and on-current etc.) are extracted from up to 80 samples of down to channel length of 50nm. Such effects are further incorporated into a surface-potential based physics compact model via calibration to experiments. Using this model, the vertical a-IGZO-FET-based 2TOC DRAM is firstly investigated with the statistical analysis of Write/Read performances, supporting device variation aware DTCO flow of future extremely large-scale and high-density M3D memory.

关键词： Semiconductor device modeling Performance evaluation Solid modeling Analytical models Statistical analysis Random access memory Feature extraction Semiconductor process modeling Device-to-device communication Three-dimensional integrated circuits

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Automatic Digital modeling for Analog Blocks in Mixed-Signal Verification

Automatic Digital Modeling for Analog Blocks in Mixed-Signal...

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2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Leng, Yangyang Ye, Zuochang Xin, Jian Wang, Zhikai Wang, Yan The Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9781665449458

Analog circuits are indispensable in practical circuit design, even in digital circuit systems. Mixed-signal circuits often cost a lot of simulation time. In this paper, we propose an automatic digital modeling algorithm to speed up the mixed-signal simulation. The algorithm is based on dynamic mode decomposition (DMD), which converts the mixed-signal circuit into a pure digital circuit. Experiments shows >100X speed-up compared with mixed-signal simulation. © 2021 IEEE.

关键词： Integrated circuit manufacture

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design and modeling for Very High-sensitivity UHF RF Energy Harvesting Circuit

Design and Modeling for Very High-sensitivity UHF RF Energy ...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Jun Yin Mircea R. Stan Department of Electrical and Computer Engineering University of Virginia Charlottesville Virginia USA

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

The increasing demand for wearable and portable IoT devices necessitates alternatives to traditional battery-powered systems, leading to the emergence of RF energy harvesting as a viable solution. However, long-distance charging poses challenges due to diminishing RF power and increased losses with distance, highlighting the critical importance of improving the sensitivity of the harvesting circuit. In this work, we propose a highly sensitive UHF RF energy harvesting circuit by optimizing a combined RF-DC rectifier (RDR) with a DC-DC converted (DDC) based on a commercial 22-nm fully-depleted silicon on insulator (FDSOI) technology. Flipped well transistors and feedback self-body biasing are used to design the RDR to adaptively tune threshold voltages while an ultra-low power frequency-adjustable feed-forward dynamic leakage suppression (FFDLS) two-phase clock generator is used for pumping the DDC to boost output DC voltage, achieving sensitivity enhancement without peripheral power overhead. Based on simulation results, our proposed circuit shows the highest sensitivity of −41.3 dBm at 1 V output under a 100 MΩ load, making it a promising candidate for ultra-low power far-field wireless charging IoT applications.

关键词： Radio frequency Sensitivity simulation Silicon-on-insulator Low power electronics Rectifiers Threshold voltage Energy harvesting Internet of Things Transistors

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帕金森神经网络建模及核团数字电路设计

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中国科学：技术科学 2024年第8期54卷 1586-1600页

作者：蔡建明包涵边逸轩徐权陈墨包伯成常州大学微电子与控制工程学院常州213159

已有的帕金森神经网络模型并未包含基底神经回路中的所有神经核团.因此,在研究发病机理和寻找最佳深部脑刺激(deep brain stimulation,DBS)的刺激靶点时忽略了其他核团潜在的影响.本文根据基底神经回路结构,利用Hindmarsh-Rose(HR)神经... 详细信息

已有的帕金森神经网络模型并未包含基底神经回路中的所有神经核团.因此,在研究发病机理和寻找最佳深部脑刺激(deep brain stimulation,DBS)的刺激靶点时忽略了其他核团潜在的影响.本文根据基底神经回路结构,利用Hindmarsh-Rose(HR)神经元模型成功构建了完整的帕金森神经网络模型.三种不同外加刺激下的数值仿真结果表明,缺失黑质致密部(substantia nigra pars compacta,SNc)核团的帕金森神经网络会出现神经元高度同步行为和异常β振荡活动,符合目前公认的帕金森发病机理,从而验证了所提的模型的合理性.此外,受生物伦理、实验难度的影响,电子神经网络更适合帕金森DBS治疗方案研究,因此,本文以SNc核团为例在现场可编程逻辑门阵列(field programmable gate array,FPGA)平台上构建了不同外加刺激下的SNc核团数字电路.电路实验结果能完整呈现出与数值仿真一致的放电行为,表明了数字电路设计的正确性.本文所设计的电路占用较低的数字电路资源,为帕金森神经网络电路实现做好基础准备.

关键词：帕金森神经网络 HR神经元模型动力学模型现场可编程逻辑门阵列(FPGA) 神经元同步

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A Stacking-Based Method for Path Loss Prediction in Evaporation Ducts

A Stacking-Based Method for Path Loss Prediction in Evaporat...

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Future Communications and Networks (FCN), International Conference on

作者： Huazheng Miao Hanzhong Zhang Tianheng Xu Ting Zhou Honglin Hu School of Microelectronics Shanghai University China Shanghai Advanced Research Institute Chinese Academy of Sciences China

ISBN: (数字)9798331512880

ISBN: (纸本)9798331512897

Evaporation duct is a common atmospheric phenomenon in marine environments, which significantly affects signal transmission. Accurately predicting path loss (PL) in evaporation ducts is crucial for the design of maritime communication systems. This paper presents an ensemble method based on stacked generalization (stacking) to predict PL in evaporation ducts. Specifically, the stacking model employs a deep neural network (DNN) as the base learner in the first layer and a random forest as the meta learner in the second layer, using meteorological and antenna parameters as inputs to predict PL values. Compared to the state-of-the-art DNN model, the mean absolute error and mean square error values of the stacking model decrease by 41.57% and 20.81%, respectively. Meanwhile, the proportion of stacking model predictions with relative errors below 1% reaches 92.02%. simulation results demonstrate that the stacking-based ensemble method outperforms single models and shows good potential for future investigations into evaporation ducts.

关键词： Radio frequency Atmospheric modeling simulation Stacking Ducts Predictive models Evaporation Numerical models Ensemble learning Maritime communications

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A Flexible Cluster Tool simulation Framework with Wafer Batch Dispatching Time Recommendation

A Flexible Cluster Tool Simulation Framework with Wafer Batc...

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IEEE International Symposium on Quality Electronic design

作者： Hsin-Ping Yen Shiuan-Hau Huang Yan-Hsiu Liu Kuang-Hsien Tseng Ji-Fu Kung Yi-Ting Li Yung-Chih Chen Chun-Yao Wang National Tsing Hua University Taiwan ROC United Microelectronics Corporation Taiwan R.O.C. National Taiwan University of Science and Technology Taiwan R.O.C.

The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulation result can also deliver messages to system engineers for achieving better throughput after adjustment. In this work, we propose a flexible simulation framework for a cluster tool. We implemented the simulator in C++ language with SystemC. The batch information used for the design of simulator was gathered from industrial data. The experimental results show that there is only less than 2% difference between the simulation and the manufacturing data in terms of entire processing time, which indicates the high accuracy of the simulator. The experimental results with the proposed dispatching method achieve a higher throughput compared to the manufacturing data such that the dispatching time points can be recommended to the system engineers.

关键词： Semiconductor device modeling Job shop scheduling Manufacturing processes Error analysis simulation Predictive models Semiconductor device manufacture

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design and simulation of Optical XNOR Logic Gate Based on MEMS Technology

Design and Simulation of Optical XNOR Logic Gate Based on ME...

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Iranian International Conference on microelectronics (IICM)

作者： Eslami, Mohamadreza Marvi, Fahimeh Dinani, Kian Jafari Shahid Beheshti Univ Fac Elect Engn Tehran Iran

ISBN: (纸本)9781665480604

Prototypes of computers, or processors, were based almost exclusively on mechanical devices. Although electronic processors have become increasingly dominant over the past few decades, Recent advances in the technology of manufacturing 3D electromechanical components in micro and nano sizes have created new techniques for building complex microstructures that are of interest to researchers in new research In the field of mechanical computing. In this paper, we present a new XNOR logic gate design approach that can be built based on micro-electromechanical logic gates. One of the main advantages of this method is the ability to combine multi-physical as well as compatibility with the CMOS manufacturing process, as well as lower power consumption compared to logic gates consisting of several CMOS transistors. In this design, we have designed and simulated an XNOR logic gate using the multi-physics capability of Comsolsoftware and as well as using optical, electronic, mechanical and electro-static physics, whose inputs will be both electrical and optical signals. In this paper, according to the above selected design, by modeling and simulating different input modes of this logic gate, we examine the effect of each mode on the output of the gate as well as other features such as structure life, power consumption and resonant frequency. The proposed gate structure has a resonant frequency of 46 kHz and is highly reliable because it can operate without mechanical connection of the MEMS operator to logic inputs.

关键词： Logic gates Optical MEMS structure Mechanical computers

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simulation of remote-controlled power supplies for laboratory and research work 16

Simulation of remote-controlled power supplies for laborator...

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IEEE 16th International Conference on the Experience of designing and Application of CAD Systems (CADSM)

作者： Sus, Bogdan B. Zagorodnyuk, Sergiy P. Bauzha, Oleksandr S. Diachuk, Nazar O. Kozinetz, Aleksey, V Taras Shevchenko Natl Univ Kyiv Inst High Technol Kiev Ukraine Taras Shevchenko Natl Univ Kyiv Fac Radio Phys Elect & Comp Syst Kiev Ukraine

ISBN: (纸本)9781665438940

The development of hardware and software for remote control systems can effectively resolve these problems. The article discusses the main steps of modeling analog and digital parts of power supplies and technical solutions for laboratory work in Multisim and Proteus. The important task of developing remotely controlled power supplies based on microcontrollers for research purposes is discussed in detail. Development is carried out by modeling the developed schemes based on digital and analog elements. The algorithm of work and the basic stages of designing the electronic circuit and methods of stabilization with the application of the microcontroller are described in detail. Software application for remote control of the power supply in real-time has been developed. The possibility of conducting remote real experiments in the courses of semiconductor electronics and peripherals was demonstrated.

关键词： Proteus remote control simulation peripheral devices high impedance samples signal encoder

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First Large-Scale (68 × 25 × 5 nm3) Atomistic modeling for Accurate and Efficient Etching Process Based on Machine Learning Molecular Dynamics (MLMD)

First Large-Scale (68 × 25 × 5 nm3) Atomistic Modeling for...

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International Electron Devices Meeting (IEDM)

作者： Zemeng Feng Ziyi Hu Tong Yu Panpan Lai Rui Ge Hua Shao Dashan Shang Zhiqiang Li Kui Xu Junjie Li Rui Chen Ling Li State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Revealing the reaction mechanisms in manufacturing advanced devices is crucial for enhancing performance at nodes below 3 nm. In this study, we introduce the first large-scale atomistic model utilizing a machine learning molecular dynamics (MLMD) framework. This model simulates the lateral isotropic selective etching process of SiO 2 /Si stack structures in Gate-all-around field-effect transistors (GAAFETs) using F* radical plasma. The dataset for this model is generated using active learning strategies based on search for F* radical reacting with Si(100) substrate. Our simulation spans $68\times 25\times 5\ \text{nm}^design$ , involving over 600,000 atoms, and demonstrates a $4\times$ improvement in model error for etching reaction trends compared to the classic molecular dynamics (CMD) method. Additionally, the model achieves a typical runtime of 16.7 hours, representing a $\sim 44.9\times$ speedup over CMD. Moreover, the simulation provides detailed reaction path and uncovers the mechanisms behind lateral etching. This framework paves the way for potential atom-to-device multi-scale process modeling, contributing to design Technology Co-optimization (DTCO).

关键词： Performance evaluation Runtime Process modeling Machine learning Market research Etching Plasmas Manufacturing Transistors Substrates

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Determining System Level Margin through SIPI Co-simulation and Jitter Transfer Function

Determining System Level Margin through SIPI Co-simulation a...

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Electronics Packaging Technology Conference (EPTC)

作者： Fern Nee Tan Li Wern Chew Ling Li Ong Sze Lin Mak Chee Hoong Mah Client System Architecture & Engineering Intel Microelectronics (M) Sdn. Bhd. Penang Malaysia Assembly and Test Division Intel Microelectronics (M) Sdn. Bhd. Penang Malaysia

ISBN: (纸本)9798350398861

This paper investigates Signal Integrity - Power Integrity relationship using a dual reference package design and understanding high-speed interconnect circuit's behavior through Jitter Transfer Function. A dual referencing design and modeling approach is introduced to enable maximum noise coupling to differential signal traces. simulation platform that allows a quick jitter assessment with power noise injection is then built to evaluate the risk of having dual referencing design. Using Peripheral Component Interconnect Express Gen5 interconnects as a case study, the findings shown that mid-frequency power noise matters most to differential interconnects, which turned out to be correlated to its Jitter Transfer Function.

关键词： Couplings simulation Transfer functions Integrated circuit interconnections Jitter Data models Integrated circuit modeling

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