Power characterization of complex macros is essential to enable accurate RT-level power estimation. Existing characterization procedures focus on the average value of power. In this paper, we take a fresh look at this...
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Power characterization of complex macros is essential to enable accurate RT-level power estimation. Existing characterization procedures focus on the average value of power. In this paper, we take a fresh look at this problem. We propose a fast, yet accurate technique to determine a time-dependent power model, i.e., a temporal power waveform, which is able to fully characterize the power behavior of a hard macro in response to a realistic input stream consisting of typical usage patterns. Our approach is simulation-based, and resorts to a mix of high-level, fast cycle-based simulation with low-level, slow accurate simulation of the long set of input patterns. Results are extremely satisfactory, since the average error between the power waveforms generated by our tool and the exact ones is always within 1%, while the reduction in the execution time ranges between one and two orders of magnitude.
This paper treats the study of on-chip temperature compensation of a broad-band UHF VCO. Analysis, design and evaluation of IC oscillators are described. Excellent agreement between simulation and measurement is demon...
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This paper treats the study of on-chip temperature compensation of a broad-band UHF VCO. Analysis, design and evaluation of IC oscillators are described. Excellent agreement between simulation and measurement is demonstrated. The frequency deviation drift specification over a 25/spl deg/C temperature range has been reduced to <0.5 MHz within the frequency range of 470/spl sim/930 MHz.
The use of partially depleted SOI CMOS technology in mainstream ULSI can be limited by transient floating body effects, that make circuit design problematic. Time-dependent V/sub T/ is observed in circuits, leading to...
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The use of partially depleted SOI CMOS technology in mainstream ULSI can be limited by transient floating body effects, that make circuit design problematic. Time-dependent V/sub T/ is observed in circuits, leading to unusual behaviours, such as current overshoot and undershoot. In order to properly evaluate the time-dependent floating-body effects on circuit performance, it is necessary to use a model (including both carrier generation and recombination) which predicts the transient responses of single devices to various front and back gate pulses. We present an enhanced version of SOISPICE-4.4 which provides the capabilities needed to correctly simulate floating-body transient effects in partially depleted circuits. The simulations are validated through systematic measurements over a wide range of experimental conditions: carrier generation and recombination-based transients, single and dual gate, back and front gate, various gate geometries. Most experiments were conducted at low V/sub D/ (to avoid impact-ionization and self-heating, i.e., to facilitate accurate calibration of the simulator) on partially depleted NMOS transistors fabricated on UNIBOND and Low-Dose SIMOX wafers. Four families of transients have been recorded, analyzed and simulated.
As the need for higher efficiencies in semiconductor manufacturing intensifies, the importance of effective intrabay automation increases. Direct delivery overhead zero foot print intrabay automation, coupled with mic...
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As the need for higher efficiencies in semiconductor manufacturing intensifies, the importance of effective intrabay automation increases. Direct delivery overhead zero foot print intrabay automation, coupled with microstocking of WIP will be a means to maximize the throughput of fully automated fabs. Microstocking can be practically implemented in the following four ways. The first instance of microstocking is found on a process tool that has more than one Input/Output (I/O) port. Another form of microstocking is the internal tool buffer commonly found on vertical furnaces and wet processing benches. A third manifestation of microstocking is the OEM supplied small capacity WIP stocker, that is mounted directly to the front of a process tool. Overhead Zero Foot Print microstocking is the fourth choice, which uses ceiling mounted shelves integrated directly below the overhead intrabay vehicle systems. This paper is the result of investigating these automation concepts using discrete event simulation modeling. The fat, process system model is integrated with the automation system to yield insight into the effectiveness of microstocking and overhead automation. The industry generally agrees that 300 mm fabs will be highly automated; this case study explores some of the issues facing those who implement intrabay automation.
We present a method for SPICE model parameter extraction for a bipolar transistor in the active and quasisaturation modes, It uses the capabilities of the BIPOLE3 [1] simulator to enhance the optimization procedure, C...
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We present a method for SPICE model parameter extraction for a bipolar transistor in the active and quasisaturation modes, It uses the capabilities of the BIPOLE3 [1] simulator to enhance the optimization procedure, Comparisons are made between the Gummel-Poon, the VBIC95, and the SGS-Thomson microelectronics SPICE model results for I-C(V-BE), I-B(V-BE), B(I-C), f(T)(I-C), and I-C(V-CE) characteristics.
The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism, Instead, wide bit-fields containing net-values for several different ...
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The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism, Instead, wide bit-fields containing net-values for several different times are used to resolve out-of-order events, Bit-parallel operations are performed to simulate;gates at the required times, The MDP technique was originally designed to be implemented in hardware, but the current software version of the algorithm has proven to be competitive with conventional event-driven multidelay simulation, Two versions of the MDP technique are presented in this paper, fixed alignment and variable alignment, The fixed alignment algorithm provides bit-fields that are wide enough to capture any event that could occur during the simulation of an input vector, while the variable alignment algorithm uses a minimum-width bit field which is just wide enough to capture those events that could occur at an individual step in the simulation, A prototype hardware design is discussed briefly.
The numerical modeling of SiGe p-MOSFETs is presented along with results of transconductance behaviour with respect to key device design and fabrication parameters such as Si cap layer thickness and Ge mole fraction p...
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The numerical modeling of SiGe p-MOSFETs is presented along with results of transconductance behaviour with respect to key device design and fabrication parameters such as Si cap layer thickness and Ge mole fraction profile. The simulations employ the theoretically calculated effective density of states in the SiGe alloy and the mobility dependence on Ge mole fraction which accounts for surface and interface scattering effects. Copyright (C) 1996 Elsevier Science Ltd
The integration of mechanical systems and microelectronics opens many new possibilities for process design and automatic functions. After discussing the mutual interrelations between mechanical and electronic design t...
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The integration of mechanical systems and microelectronics opens many new possibilities for process design and automatic functions. After discussing the mutual interrelations between mechanical and electronic design the different ways of integration within mechatronic systems and the resulting properties are described. The information processing can be organized in multilevels, ranging from low-level control, through supervision to general process management. In connection with knowledge bases and inference mechanisms intelligent control systems result. The design of control systems for mechanical systems is described, from modeling, identification to adaptive control for nonlinear systems. This is followed by solving supervision tasks with fault diagnosis. Then design tools for mechatronic systems are considered and examples of applications are given, like intelligent control of an electromechanical throttle actuator and force and torque reconstruction for a robot.
designing, verifying and testing microsystems and microsystem-components will not be feasible without the intensive use of design methodologies and supporting computer aided design tools. Requirements Engineering at t...
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designing, verifying and testing microsystems and microsystem-components will not be feasible without the intensive use of design methodologies and supporting computer aided design tools. Requirements Engineering at the beginning of a top down design flow results in formal specifications for the desired system and component behavior and a list of design constraints. These are the basis for documentation as well as for modeling, system simulation, parameterized component design and hardware/software-codesign. Finite Element Analysis and simulations on various levels of abstraction are necessary to characterize parameterized functions (e.g. sensors and actuators built on different microtechnologies and materials) and generate macromodels in a bottom up design flow to verify each design step for component integration, system integration, packaging and interconnects, especially dealing with parasitics and cross sensitivities.
Verified/predictive modeling has become an integral part of electronic packaging product development in order to reduce costs and cycle time. In this paper, interferometric displacement measurement methods are utilize...
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Verified/predictive modeling has become an integral part of electronic packaging product development in order to reduce costs and cycle time. In this paper, interferometric displacement measurement methods are utilized to verify the validity of numerical models for microelectronics packaging design. Three optical methods with submicron sensitivities are employed: moire interferometry, microscopic moire interferometry and Twyman/Green interferometry. The first two provide contour maps of in-plane displacement fields, and the third maps out-of-plane displacement fields. Their high sensitivity and high spatial resolution make them ideally suited for verification of numerical models. By combining numerical modeling and experimental verification until the results merge, numerical models become more accurate and dependable. Then, the models cart be applied extensively to optimize the package designs with confidence that the models provide effective information on material and geometry sensitivity.
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