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检索条件"任意字段=Design, Modeling, and Simulation in Microelectronics"

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PANNE: a parallel computing engine for connectionist simulation

PANNE: a parallel computing engine for connectionist simulat...

引用

International Conference on microelectronics for Neural Networks

作者： I.Z. Milosavlevich B.G. Flower M.A. Jabri Systems Engineering and Design Automation Laboratory Department of Electrical Engineering University of Sydney Sydney NSW Australia

PANNE (Parallel Artificial Neural Network Engine) is a parallel computing engine aimed at delivering super-computing power to numerical applications such as connectionist simulation and signal processing. The PANNE system exploits the features of the TMS320C40 DSP chip which make it suitable for building parallel computing systems. PANNE has been built with flexibility in mind; it is expandable in terms of hardware resources and supports both shared and distributed memory programming paradigms. We estimate that a system of 16 DSPs would be capable of delivering up to 80/spl times/10/sup 6/ connection updates per second.

关键词： Parallel processing Engines Digital signal processing chips Computational modeling Signal processing algorithms Computer architecture Signal processing Digital signal processing Acceleration Workstations

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An approach for integrated specification and design of real-time systems

An approach for integrated specification and design of real-...

引用

European design Automation Conference

作者： Y. Tanurhan S. Schmerler H.-P. Golz K.D. Muller-Glaser Department of Electronic Systems and Microsystems FZL/ESM Forschungszentrum Informatik Karlsruhe Karlsruhe Germany

A design methodology for the design of microelectronic systems which includes hardware and software for open loop and closed loop control is presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real time capabilities, the environment presented gives special consideration to these constraints. We give an example for concrete applications, which shows, how the design of real time embedded systems is supported by the design methodology and environment.

关键词： design methodology Embedded system Real time systems microelectronics Hardware Open loop systems Control systems Computational modeling Analytical models Concrete

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Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

Hierarchical statistical characterization of mixed-signal ci...

引用

IEEE International Conference on Computer-Aided design

作者： E. Felt S. Zanella C. Guardiani A. Sangiovanni-Vincentelli Electrical Engineering and Computer Sciences University of California Berkeley CA USA Elettronica ed Informatica Università degli Studi di Padova Padova Italy Central Research and Development D.A.I.S. SGS-Thomson Microelectronics Agrate Italy

A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.

关键词： Monte Carlo methods Performance analysis Circuit simulation Statistical distributions Covariance matrix Circuit testing design methodology Analysis of variance Response surface methodology Research and development

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Integrated design process with MESA/MERLAN

Integrated design process with MESA/MERLAN

引用

IEEE International Symposium on Computer Aided Control System design (CACSD)

作者： Y. Tanurhan S. Schmerler K.D. Muller-Glaser Department of Electronic Systems and Microsystems F Z I Computer Science Research Center Karlsruhe Karlsruhe Germany

In this paper, a methodology for the design of microelectronic systems which include hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real-time capabilities, the environment presented gives special consideration to these constraints. For verification purpose of the developed design and specification methodology a software prototype has been implemented and used in concrete example applications, which is also presented in this paper.

关键词： Process design design methodology microelectronics Hardware Open loop systems Control systems Computational modeling Analytical models Embedded system Real time systems

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A tree matching chip

A tree matching chip

引用

International Conference on VLSI design

作者： V. Krishna A. Ejnioui N. Ranganathan Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa FL USA

Tree matching is an important problem used for 3D object recognition in image understanding and vision systems. It is also used in the design of on-line interpreter systems as well as code optimization in compilers. The objective of tree matching is to find the set of nodes at which a pattern tree matches a subject tree. Recently, two linear systolic array algorithms have been proposed by the authors. In this paper, we propose an improved approach wherein the the systolic algorithm is based on a linear array of fixed size independent of the problem size and larger strings are partitioned and processed based on the array size. Also, the architecture is simplified by moving the logic for processing variables in each PE to a single PE attached at the end. The systolic algorithm and architecture have been verified through simulation using the Cadence design tools.

关键词： Pattern matching Partitioning algorithms Computational modeling Terminology Object recognition Optimizing compilers Systolic arrays Logic Parallel algorithms Concurrent computing

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BiMOS modeling for reliable SOI circuit design

BiMOS modeling for reliable SOI circuit design

引用

IEEE SOI-3D-Subthreshold microelectronics Technology Unified Conference (S3S)

作者： S. Krishnan J.G. Fossum M.M. Pelella University of Florida Gainesville FL USA IBM Corporation Hopewell Junction NY USA

Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits operating at voltages well below the BJT-defined drain-source breakdown. The BJT is also critically important with regard to soft errors in low-voltage SOI memory circuits. In these cases, the BJT current is driven by dynamic charging of the body and concomitant forward biasing of the source (or drain) junction, supported by capacitive, or charge coupling between the BJT and the MOSFET. A reliable circuit model for the floating-body SOI MOSFET must therefore account for the coupled BJT. In this paper we present a new, quasi-2D parasitic BJT model physically coupled to the SOISPICE MOSFET models and defined in terms of their parameters. We further use physical insight derived from this BiMOS modeling to identify a new means of controlling the transient BJT, or leakage current in SOI MOSFETs which could be exploited in design.

关键词： Circuit synthesis Silicon germanium Germanium silicon alloys Parasitic capacitance MOSFETs Medical simulation Radiative recombination Leakage current Random access memory Circuit simulation

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Combined control flow dominated and data flow dominated high-level synthesis

Combined control flow dominated and data flow dominated high...

引用

design Automation Conference

作者： E. Berrebi P. Kission S. Vernalde S. De Troch J.C. Berluison J. Frehel A.A. Jerraya I. Bolsens Av. Félix Viallet TIMA 46 Grenoble France SGS-Thomson Microelectronics Inc. France IMEC Leuven Belgium

This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility.

关键词： High level synthesis Communication system control Codecs Motion estimation Protocols Throughput Data flow computing Circuit synthesis Computational modeling Circuit simulation

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Non-quasi-static SOI MOSFET model dedicated for analog circuit design

Non-quasi-static SOI MOSFET model dedicated for analog circu...

引用

IEEE SOI-3D-Subthreshold microelectronics Technology Unified Conference (S3S)

作者： E. Robilliart E. Dubois IEMNIISEN UMR CNRS D'Ascq France

A one-dimensional CAD-oriented SOI MOSFET model continuous over all regions of operation is described. This model is valid for long and short channel fully depleted devices. In addition, the NQS nature of the charge redistribution is implicitly accounted for, without using any empirical partition of the channel charge. The physical and numerical foundation of our model is first described. In a second part, we propose a quantitative comparison between our modeling approach and two-dimensional device simulation. A circuit application is given in a third part. Finally, current memory cells (a circuit particularly sensible to charge injection) are simulated with this new model.

关键词： MOSFET circuits Analog circuits Circuit simulation Voltage Strips Capacitance Poisson equations Dielectrics Scalability Silicon on insulator technology

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Optimization of custom MOS circuits by transistor sizing

Optimization of custom MOS circuits by transistor sizing

引用

IEEE International Conference on Computer-Aided design

作者： A.R. Conn P.K. Coulman R.A. Haring G.L. Morrill C. Visweswariah IBM Microelectronics Division IBM Thomas J. Watson Research Center USA

Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed.

关键词： MOSFETs Circuit optimization Circuit simulation design optimization Delay effects Minimax techniques Large-scale systems Packaging Lagrangian functions Computational modeling

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Simultaneous switching noise projection for high-performance SOI chip design

Simultaneous switching noise projection for high-performance...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified Conference (S3S)

作者： I.K. Wang H.H. Chen IBM Reasearch Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA

This paper describes the circuit modeling techniques to predict on-chip simultaneous switching noise for high performance SOI circuits. The analysis includes both the inductive /spl Delta/I noise on the package level and the resistive I R drop on the chip level. By identifying the hot spots on the chip and /spl Delta/V across the chip, designers can optimize the placement of on-chip decoupling capacitors and effectively minimize the switching noise for SOI chips.

关键词： Chip scale packaging Circuit noise Silicon on insulator technology Switching circuits CMOS technology Capacitance Power supplies Delay estimation Circuit simulation Voltage

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