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Bipolar/BiCMOS Circuits and Technology Meeting

作者： Niu Ruan Tang Institute of Microelectronics Fudan University Shanghai China ASIC and System Laboratory Shanghai China

The current and charge relations for SiGe-base heterojunction bipolar transistor (HBT) are derived from the differential equations for carriers in the base. A universal description for all injection levels is obtained, which is suitable for circuit simulation. Based on these relations, the invalidity of the concept of effective doping used previously in high injection is identified and explained physically. The base profile design for applications at both room and liquid nitrogen temperature is also discussed.

关键词： Heterojunction bipolar transistors

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General purpose simulated annealing on hardware

General purpose simulated annealing on hardware

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IEEE Winter Workshop on Nonlinear Digital Signal Processing

作者： J. Niittylahti H. Raittinen K. Kaski Microelectronics Laboratory Tampere University of Technology Tampere Finland

A general purpose hardware for the Simulated Annealing optimization method has been designed and implemented. It is a digital stand-alone system that requires no host computer. The prototype design utilizes a full custom VLSI random number generator chip among standard digital circuits. Altera's reprogrammable FPGA technology is used to increase the packing density and to allow modifications. Thisfast optimization tool call be used to optimize any dynamically configurable hardware to adapt a given task. All application example and performance estimations are also presented.

关键词： Simulated annealing Hardware Cost function Temperature Circuit simulation Random number generation Computational modeling Solid modeling Optimization methods microelectronics

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Numerical simulation of Non-Volatile Memories

Numerical Simulation of Non-Volatile Memories

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European Conference on Solid-State Device Research (ESSDERC)

作者： C. Lombardi S. Keeney R. Bez L. Ravazzi D. Cantarelli F. Piccinini A. Concannon A. Mathewson THOMSON Microelectronics S.G.S. Microelettronica S.p.A Milan Italy NMRC University College Cork Ireland SGS-ThOMSON Microelectronics Agrate Brianza (MI) Italy

The trend towards ever decreasing geometries is making the non-volatile memory cell design task increasingly difficult. For reduced cost and time to market, simulation tools are essential to reduce the number of experiments on silicon wafers which are becoming increasingly expensive due to the increase in process complexity with each new generation [1]. A general purpose two-dimensional device simulator which allows the complete transient simulation of non volatile memories has been developed. Three models were identified which were necessary to simulate the electrical characteristics of EPROM, EEPROM and flash-EEPROM devices. These were Fowler-Nordheim tunneling, Band-to-Band tunneling and hot electron injection. All three models were incorporated into the drift-diffusion and hydrodynamic device simulator HFIELDS [2,3]. The models were carefully validated with appropriate measurements from test structures and devices. The enhanced program represented the first complete tool capable of modeling all the most important effects in floating gate memory devices.

关键词： Numerical simulation Nonvolatile memory EPROM Tunneling Geometry Costs Time to market Silicon Semiconductor device modeling Electric variables

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Mechanical and materials modeling/simulation/verification trend for electronics packaging products

Mechanical and materials modeling/simulation/verification tr...

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Electronic Components and Technology Conference (ECTC)

作者： C.K. Lim Endicott Electronics Packaging Technology Products IBM Corporation Endicott NY USA

Theoretical modeling and simulation have been used to address stress/strain related issues in microelectronics packages. Over time, the emphasis has moved from the problem solving mode to the predictive mode. With ever shrinking development schedules, the need to verify the validity of these models has become increasingly important. Although numerical modeling tools and algorithms have improved significantly over the years, recent advances in micromechanical and photomechanical tools have been the key in verifying the model leading to an enhanced and realistic model. This paper reviews some of the latest developments in micromechanical and photomechanical devices with up to 20 nm displacement sensitivity capability. Several examples of their implementation in an electronics packaging development environment will be presented. These verification tools lead to more accurate and realistic models, which in turn, facilitate design optimization at an early stage.< >

关键词： Electronics packaging Optical interferometry Predictive models Micromechanical devices Computational modeling Holography Holographic optical components Optical sensors Capacitive sensors Problem-solving

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An integrated system for design automation of VLSI interconnects and packaging

An integrated system for design automation of VLSI interconn...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： P. Hsu J.W. Rozenblit S.N. Pratapneni C.M. Wolff J.L. Prince Center for Electronic Packaging Research Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

The packaging design support environment (PDSE) is a software system being developed at the University of Arizona to facilitate the analysis and design of packaging structures for microelectronic integrated circuits, a subject which is becoming one of increasing importance with higher circuit integration and system performance. PDSE provides a platform for work in several active research areas including interconnect and packaging modeling and simulation in electrical, thermal, and thermal-mechanical aspects, CAD framework development and evaluations for performance, manufacturability, and reliability, etc. This paper describes the overall architecture and characteristics of the PDSE system in development, its implementation and applications.< >

关键词： design automation Very large scale integration Integrated circuit packaging Integrated circuit interconnections Software packages Software systems Performance analysis microelectronics System performance Circuit simulation

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Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology

Non-local modeling of impact ionization for optimal device/c...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified Conference (S3S)

作者： S. Krishnan J.G. Fossum Department of Electrical Engineering University of Florida Gainesville FL USA

Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS.< >

关键词： Impact ionization Predictive models MOSFETs Semiconductor device modeling Ultra large scale integration Electric breakdown Latches Physics Circuit simulation design optimization

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Packaging and interconnection techniques for microsystems

Packaging and interconnection techniques for microsystems

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IEEE International Conference on Systems, Man and Cybernetics

作者： H. Reichl FSP-Technologien der Mikroperipherik Technical University Berlin Berlin Germany

Microsystems require packaging and chip interconnection techniques for system integration. Electrical, optical, thermal and mechanical signal paths have to be realized. System integration techniques determine parameter interactions and signal interferences within the system. Therefore critical packaging and interconnection elements in a microsystem have to be characterized and considered in system simulation. This causes the development of new simulation and design techniques. Furthermore, precise and reproducible mounting, bonding and encapsulation techniques are important for optimized systems. The introduction of new packaging architectures has to increase the technical performance and to lower the packaging costs for microsystems. Biological models are helpful for the development of new packaging and interconnection techniques.< >

关键词： Packaging Integrated circuit interconnections Integrated circuit technology microelectronics Biological system modeling Actuators Silicon Water heating Costs Ceramics

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design methodology for low power, high-speed CMOS devices utilizing SOI technology

Design methodology for low power, high-speed CMOS devices ut...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified Conference (S3S)

作者： A. Yoshino K. Kumagai S. Kurosawa H. Itoh K. Okumura ULSI Device Development Laboratories NEC Corporation Limited Sagamihara Japan

We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability.< >

关键词： design methodology Circuit simulation SPICE Parasitic capacitance CMOS technology Delay estimation Semiconductor device modeling Voltage Energy consumption Propagation delay

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OpAmp Macromodel design Techniques for EMI Effects simulation

OpAmp Macromodel Design Techniques for EMI Effects Simulatio...

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10th International Zurich Symposium and Technical Exhibition on Electromagnetic Compatibility

作者： D. Golzio S. Graffi M. V. Kovács G. Masetti Fallmerayerstrasse 7 8000 Munich 40 - Germany Università di Bologna - D.E.I.S. Viale Risorgimento 2 40136 Bologna - Italy

ISBN: (纸本)9781509031955

This paper describes the design techniques adopted to define OpAmp macromodels to be used with circuit simulators (SPICE or similar) for EMI-effects analysis and prediction. The first step consists in the analysis and evaluation, assisted by computer simulations, of some characteristics of the OpAmp device-level model, in order to obtain a good understanding of the OpAmp basic features and performances. A first draft of the EMI-macromodel is issued. Then the EMI-macromodel elements are adjusted by comparing the simulations of some typical OpAmp characteristics with both the device-level model and the EMI-macromodel. The EMI-macromodel behaviour is lastly assessed and validated with experimental measurements including susceptibility cases. As examples, the results obtained for the 741 and the LF355 OpAmp's are presented.

关键词： Integrated circuit modeling Frequency measurement Voltage measurement microelectronics Electromagnetic interference Transistors Standards Topology SPICE Resistors

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AN ENHANCED SPICE MOSFET MODEL SUITABLE FOR ANALOG APPLICATIONS

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IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 1992年第11期11卷 1418-1425页

作者： POWER, JA LANE, WA National Microelectronics Research Centre University College Cork Cork Ireland

A MOSFET model optimized for analog circuit simulation is presented and shown to agree with measured device characteristics, especially device output conductance and transconductance, over a wide range of operation. The widely used SPICE Level 3 (MOS3) model equations were utilized as a starting point in the model development process. The enhanced model (NMOD) exhibits smooth and continuous transitions in the weak to strong inversion region, and also in the region between linear and saturation modes of device operation. These smooth transitions improve both the model's current and conductance prediction accuracy, as well as its convergence properties when employed in circuit simulation. This is made possible because a single current equation is utilized for all regions of device operation. The NMOD model accurately characterizes devices over a wide range of geometries, achieving for example 1.3% and 4.2% average errors between measured and modeled I(DS) and gds characteristics, respectively, for a 20/1.3-mum p-channel device over a 5-V bias range.

关键词： SPICE MOSFET circuits Circuit simulation Equations Solid modeling Analog circuits Transconductance Predictive models Accuracy Convergence

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