This conference proceedings contains 121 papers on electronic design automation. Topics discussed include the design of asynchronous controllers, the design of CMOS VLSI circuits, parallel algorithms for speeding up c...
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ISBN:
(纸本)0818627808
This conference proceedings contains 121 papers on electronic design automation. Topics discussed include the design of asynchronous controllers, the design of CMOS VLSI circuits, parallel algorithms for speeding up cell placement on a computer network, timing issues in high-level synthesis, verifying the correctness of concurrent controllers, microarchitecture synthesis, timing analysis and verification, combinational logic synthesis, systems engineering and mechatronics, top-down physical design, rapid prototyping with field programmable gate arrays, finite state machine design, routing problems, automatic test generation, scheduling and allocation, topological optimization in routing, design for testability, circuit-level analysis, fault simulation, system and information modeling, design error detection and location, testing using current profiles, unifying data for CAD frameworks, generic systems for statistical circuit design, and high-level digital design with the VHDL hardware description language.
Many of the advances that have been made beyond SPICE, associated with the Saber simulator and the analog hardware description language MAST, are described. Saber is a comprehensive simulator spanning analog and digit...
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Many of the advances that have been made beyond SPICE, associated with the Saber simulator and the analog hardware description language MAST, are described. Saber is a comprehensive simulator spanning analog and digital domains and capable of simulating systems described by a mixture of models at the primitive, functional, and behavioral levels. MAST allows the architectural separation of modeling and simulation in the Saber environment. Similarities and differences between the simulation algorithms in Saber and SPICE are presented.< >
A central issue in the solution of many computer aided design problems is finding a concise representation for circuit designs and their functional specifications. Ordered binary decision diagrams (OBDDs) have recentl...
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A central issue in the solution of many computer aided design problems is finding a concise representation for circuit designs and their functional specifications. Ordered binary decision diagrams (OBDDs) have recently emerged as a popular representation for various CAD applications such as design verification, synthesis, testing, modeling and simulation. Unfortunately, there is no efficient OBDD representation for many circuits, even in some cases for circuits which perform such apparently simple functions as multiplication. The authors present a new BDD representation scheme, called indexed BDDs (IBDDs), and show that it allows polynomial representations of functions which provably require exponential space using OBDDs. The key idea in IBDDs is to allow multiple occurrences of the input variables, subject to ordering constraints. The authors give an algorithm for verifying the equivalence of two IBDDs and a heuristic for constructing IBDDs for arbitrary combinational circuits.< >
CAzM (Circuit Analyzer with Macro-modeling) is a robust, table-based analog circuit simulator employing modern numerical techniques to improve convergence and operating efficiency. It allows devices to be modeled via ...
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CAzM (Circuit Analyzer with Macro-modeling) is a robust, table-based analog circuit simulator employing modern numerical techniques to improve convergence and operating efficiency. It allows devices to be modeled via current and charge vs. voltage tables for minimal CPU usage, or analytic function calls may be used directly for maximum accuracy. CAzM 5.0 will be discussed here, outlining new features as well as performance data compared to HSPICE.
Presents the design of an integrated circuit, with a pipeline architecture, supporting programmable recursive filters intended for optimal edge detection of 2D images. The circuit is designed and simulated in 1.5 mu C...
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Presents the design of an integrated circuit, with a pipeline architecture, supporting programmable recursive filters intended for optimal edge detection of 2D images. The circuit is designed and simulated in 1.5 mu CMOS technology using microelectronics computer aided design: COMPASS. This CAD contains all necessary tools (datapath library, timing verification, chip compiler. . .) for a successful design. This circuit can process up to 1024*1024 8-bit images at a 20 MHz pixel frequency.< >
A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effec...
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A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effective for suppressing drain induced barrier lowering (DIBL) of buried channel pMOSFETs, without any degradation in Vt controllability. simulation results suggest the potential profile engineering is useful for designing 0.25 mu m buried channel pMOSFETs with high driving capability and good Vt controllability.< >
A three-dimensional (3-D) general-purpose device simulator is presented, and issues related to its geometrical flexibility and computational efficiency are discussed. Triangular-based prismatic elements are used as bu...
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A three-dimensional (3-D) general-purpose device simulator is presented, and issues related to its geometrical flexibility and computational efficiency are discussed. Triangular-based prismatic elements are used as building blocks for the discretization of device equations, providing a reasonable tradeoff between simplicity and geometrical flexibility. Suitable numerical techniques, including a "local-solution" algorithm, have been implemented in order to improve the computational efficiency of the code. A general treatment has been devised to handle floating-gate devices, which allows the program to cope with complex structures, such as the dual EPROM structure discussed in Section II. Finally 3- and 2-D simulation results are compared whenever possible.
Although preserving the hierarchy in compiled simulation can significantly reduce the compilation time for the code generated by the circuit compiler, the possibility of introducing pseudocycles due to element groupin...
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Although preserving the hierarchy in compiled simulation can significantly reduce the compilation time for the code generated by the circuit compiler, the possibility of introducing pseudocycles due to element grouping can impair the performance of the generated code. A new approach to this problem is presented which uses dependency information to reduce the number of times a particular block must be simulated. The problem of determining the minimum schedule is shown to be NP-complete, and a set of heuristics for the problem is presented. Experimental results for different combinations of these heuristics are presented. Finally, an algorithm for determining dependency information from the contents of a block is presented.
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