A computer-aided-design (CAD) architecture for microelectromechanical systems is presented in which conventional mask layout and process simulation tools are linked to three-dimensional mechanical CAD and finite-eleme...
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A computer-aided-design (CAD) architecture for microelectromechanical systems is presented in which conventional mask layout and process simulation tools are linked to three-dimensional mechanical CAD and finite-element tools for analysis and simulation. The architecture is exercised at an elementary level by modeling the first steps of the MIT baseline CMOS process. An architecture for an object-oriented material property simulator is shown in which material properties and their process dependence are stored and are accessed based on the specific process conditions.< >
The authors propose the use of data compression hardware to improve the performance of a relational database machine. They derive detailed analytical models of a specific relational database machine DELTA and report s...
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The authors propose the use of data compression hardware to improve the performance of a relational database machine. They derive detailed analytical models of a specific relational database machine DELTA and report simulation results that quantify the improvement in its system performance due to compression hardware. The main contribution of the present work is the strategy of using compression hardware in the design of database machines to overcome the I/O bottleneck, thereby increasing their performance. The authors suggest the use of on-the-fly hardware to compress and decompress the data so that the time overhead due to compression is negligible.< >
A pole-zero simulator with a component sensitivity analysis function has been developed in order to achieve high-performance characteristics in analog circuits. The functions of this simulator include specifying the c...
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A pole-zero simulator with a component sensitivity analysis function has been developed in order to achieve high-performance characteristics in analog circuits. The functions of this simulator include specifying the circuit components which determine pole-zero values and intensity computation for the influence of individual components on such circuit characteristics as DC-gain, unity-gain frequency, etc. This simulator provides very straightforward design flow. In an op-amp design example, frequency response is seen to improve greatly without trial and error.< >
A compact SPICE model to stimulate an EPROM cell is presented. Starting from the physics-based MOS model and taking into account impact ionization and the parasitic bipolar effect, 'avalanche' leading to snap-...
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A compact SPICE model to stimulate an EPROM cell is presented. Starting from the physics-based MOS model and taking into account impact ionization and the parasitic bipolar effect, 'avalanche' leading to snap-back is described. Gate current, based on the 'lucky-electron' model, is integrated in one dimension along the channel. The floating gate voltage is induced by external biases and trapped charges. Threshold voltage as seen from the control gate is considered. Results from simulations of transient behavior during writing and reading operations are shown; they were satisfactorily used for the submicron cell in the design of the 16 megabit EPROM.< >
Techniques for the design of high-resolution digital-to-analog converters (DACs) that use precision-matched components are described. Statistical models, based on test chip data, that realistically describe both local...
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Techniques for the design of high-resolution digital-to-analog converters (DACs) that use precision-matched components are described. Statistical models, based on test chip data, that realistically describe both local mismatches and longer range spatial correlations are investigated. These models have been incorporated into a special-purpose DAC analysis/simulation tool (DACSIM) to provide a powerful Monte-Carlo yield estimation capability. DACSIM also performs accurate DC simulation of a large class of resistor-network DAC circuits taking into account many important parasitic effects, including superposition nonlinearities. An error-corrected DAC architecture that uses the concept of a generalised decoding strategy programmable at test has been validated in a CMOS 13 bit segmented current-switched DAC. The approach exhibits the potential for attaining very high accuracy without trimming.< >
A technique for the determination of two-dimensional impurity profiles in silicon using methods for emission computed tomography is presented. Several one-dimensional impurity profiles obtained for different direction...
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A technique for the determination of two-dimensional impurity profiles in silicon using methods for emission computed tomography is presented. Several one-dimensional impurity profiles obtained for different directions through the sample are used to reconstruct the two-dimensional profile. A simulation study of the experiment is described, and effects of various experimental and reconstruction parameters are discussed. Reconstructions of an area of 4 mu m*4 mu m from thirteen one-dimensional measurements, with a resolution of 1000 AA, are numerically possible.< >
The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast to the conventional circuit simulators which employ a built...
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ISBN:
(纸本)0897913108
The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast to the conventional circuit simulators which employ a built-in model library approach, iSMILE generates and links all the necessary codes automatically from a minimal set of model descriptions contained in a user's model input *** are completely shielded from the internal complexity of the program when implementing new models. This flexibility of extraction and by comparing circuit simulation results in terms of performance and *** has been used successfully as a CAD tool for the development of new models for high-speed optoelectronic integrated circuits.
PEPPER is a computer program that simulates in one dimension the ion implantation, diffusion, oxidation, epitaxy, deposition, and etch processes used in VLSI technology. The program contains an efficient Monte Carlo i...
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PEPPER is a computer program that simulates in one dimension the ion implantation, diffusion, oxidation, epitaxy, deposition, and etch processes used in VLSI technology. The program contains an efficient Monte Carlo ion implantation algorithm that includes explicit calculation of ion channeling and damage. The key feature of the diffusion calculation is a general partial differential equation solver for rapid prototyping of physical models. The solver has been used to develop several unique diffusion models. A novel model for impurity diffusion in polysilicon treats the problem as a two-stream process, with relatively slow standard diffusion within the grain and a much more rapid component of diffusion along the grain boundaries. The two components are coupled at each point by a segregation term. Two other models for impurity diffusion in silicon include explicit calculation of the coupling of point defects with impurities. One of the point-defect models is a general and detailed formulation from a chemical kinetics viewpoint, while the other makes further assumptions to simplify the model for engineering analysis.< >
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