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检索条件"任意字段=Design, Modeling, and Simulation in Microelectronics"

共 1684 条记录，以下是171-180 订阅

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Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level simulation

Machine Learning-Assisted Single-Event Transient Model of 12...

引用

International Conference on ASIC

作者： Jianwen Lin Linlin Cai Yutao Chen Haoyu Zhang Wangyong Chen School of Microelectronics Science and Technology Sun Yat-sen University Guangzhou China Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-sen University Guangzhou China

As the geometries of transistors continue to scale down, single-event transient (SET) are becoming a major source of soft errors in circuit design. This paper proposes a machine learning method for modeling SET in circuit-level simulations with the high efficiency, since traditional models such as the double exponential model are not coupled with circuit responses. The proposed artificial neural network (ANN) model shows a great prediction accuracy for single-event transient currents in 12nm FinFET technology under different time, linear energy transfer (LET), bias voltage, and strike positions. The trained model can be implemented into SPICE with Verilog-A for circuit-level simulation, and its validity in a 7-stage inverter chain and a 6T SRAM are demonstrated to provide the rapid guidance for radiation reliability.

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Reliability Study of Various Edge Terminations of Silicon Carbide Power Devices Using simulation Methods

Reliability Study of Various Edge Terminations of Silicon Ca...

引用

Electronic Information Engineering and Computer Technology (EIECT), International Conference on

作者： Wenbo Yue Jia Liu Zheng Zhang Cairong Huang Nengjie Huo School of Microelectronics South China Normal University Foshan China Technology Development Ascen Power Semiconductor Co. LTD. Guangzhou China

ISBN: (数字)9798331528850

ISBN: (纸本)9798331528867

Reliability is one of the major concerns for SiC devices. A proper edge termination structure would enable SiC devices to operate at designed voltages because it mitigates the electric field aggregation caused by the cylindrical or spherical junctions. However, a great number of research has been reported on studying the optimization of edge terminations to achieve higher breakdown voltage (BV). In contrast, research on the impact of edge termination design on devices' reliability remains limited. In this work, floating field ring (FFR), single-zone junction termination extension (SZ-JTE), ring-assisted JTE (RA-JTE), multi-floating zone JTE (MFZ-JTE), and Hybrid-JTE are studied. Their reliability performance is evaluated by comparing the BV stability of these termination designs under different implantation doses, critical dimension (CD) deviations, and fixed SiC/SiO 2 interface charge through technology computer-aided design (TCAD) simulations. Among all the edge terminations listed, Hybrid-JTE has exhibited a champion reliability.

关键词： Performance evaluation Analytical models Silicon carbide Computational modeling Reliability engineering Stability analysis Silicon Robustness Reliability Junctions

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Channel modeling of Multilayer PCB with Nonhomogeneous Substrates using Neural Network 13

Channel Modeling of Multilayer PCB with Nonhomogeneous Subst...

引用

13th International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021

作者： Wang, Xin Chen, Xiong Wang, Ling Tianjin University School Of Microelectronics Tianjin China

ISBN: (纸本)9781665434379

This paper proposes a simplified channel modeling method for the multilayer PCB with nonhomogeneous substrate filling using neural network. The neural network model is used to obtain a simplified relationship between the geometry parameters at section view and the resistance, inductance, conductance and capacitance (RLGC) of the multilayer PCB. By using this method, the S-parameter comparable with finite element electromagnetic (EM) simulation can be obtained. By this proposed method, the channel property of multilayer PCB filling with nonhomogeneous substrates can be effectively solved rather than using the time- costing full wave simulation. © 2021 IEEE.

关键词： Timing circuits

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Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package

Board level FEA reliability and stress modeling for chip-to-...

引用

Electronic Components and Technology Conference (ECTC)

作者： Rathin Mandal Chai Tai Chong Institute of Microelectronics Agency for Science Technology and Research (A*STAR) Innovis Singapore

Chip-to-wafer interconnect approach is to produce denser and smaller dies, while improving inter-chip bandwidth and power dissipation. In this work a vertical system integration is done by copper pillar and solder interconnects. Three-dimensional (3D) integration technology uses chip-to-wafer bonding to achieve effective chip integration. By structural simulation and modeling a reliable package selection is made from different package designs, epoxy mold compounds (EMC), polymer dielectric (PD) materials and different other package parameters. In this simulation and modeling an approach has been taken to model two levels of solder interconnects namely copper pillar solder micro-bump and BGA (ball grid array) solder in the same FEA (finite element analysis) model. FEA mesh densities in 1 st and 2 nd interconnects are joined by contact pair definition. Parametric studies are done for three different EMC and three different PD materials. 1 st level solder interconnect or micro-bump temperature cycling (TC) reliability life is significantly higher than 2 nd level solder interconnect due to presence of EMC around the 1 st level interconnect. High CTE (coefficient of thermal expansion) of EMC shows very poor solder life for 1 st level solder interconnect. PD material CTE shows significant impact on component side solder life for 2 nd level interconnect. Also, higher PD material CTE shows worsening 1 st level interconnect life. Stress analysis shows pad diameter smaller than UBM (under bump metallization) opening is a better design.

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Sallen-Key High-Pass Filter with Unrelated Tune of Generic Parameter 23

Sallen-Key High-Pass Filter with Unrelated Tune of Generic P...

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23rd IEEE International Conference of Young Professionals in Electron Devices and Materials, EDM 2022

作者： Denisenko, Darya Yu. Prokopenko, Nikolay N. Ivanov, Yuri I. Butyrlagin, Nikolay N. Don State Technical University Department of Scientific Research Rostov-on-Don Russia Southern Federal University Department of Automatic Control Systems Rostov-on-Don Russia Department of Information Systems and Radio Engineering Don State Technical University Zelenograd Rostov-on-Don Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Zelenograd Rostov-on-Don Russia

ISBN: (纸本)9781665498043

New second order high-pass filter of the Sallen-Key family circuit is considered, where there is unrelated tune of generic parameters by a digitally controlled resistor - the pole frequency, Q-factor pole and the scale transfer coefficient. The basic mathematical expressions of transfer function for proposed high-pass filter are obtained. A comparison of the parameters of the known and new schemes is given. A Sallen-Key high-pass filter circuit based on a high-frequency emitter follower has been developed. The results of high-pass filter modeling in the Micro-Cap 12 environment using the OP37 operational amplifier and an ideal buffer amplifier are presented. Computer simulation has shown that the pole frequency is adjusted by resistor R5. Adjusting the pole attenuation is possible by changing the resistor R3, while the pole attenuation frequency unchanged, an increase in R3 leads to an increase of the pole attenuation. © 2022 IEEE.

关键词： Operational amplifiers

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modeling and simulation of Terahertz Indoor Wireless Channel Based on Radial Basis Function Neural Network 13

Modeling and Simulation of Terahertz Indoor Wireless Channel...

引用

13th International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021

作者： Guo, Yating Liu, Yuanjian Li, Shuangde Nanjing University Of Posts And Telecommunication College Of Electronic And Optical Engineering College Of Microelectronics Jiangsu Nanjing210003 China

ISBN: (纸本)9781665434379

This paper studies the radial basis function (RBF) neural network algorithm, applying big data analysis to the latest developments in wireless communication and channel modeling. A channel model based on RBF neural network is proposed to predict the path loss and delay spread of the wireless channel in indoor environment at 350/ 650 GHz. It is found that the mean square error (MSE) is within 10-4 at different frequencies. © 2021 IEEE.

关键词： Mean square error

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W-band Broadband Frequency Multiplier

W-band Broadband Frequency Multiplier

引用

IEEE Asia-Pacific Conference on Antennas and Propagation (APCAP)

作者： Xi Fang Bo Zhang Zhongqian Niu Yuanbo Wen Lei Wang School of Optoelectronic Engineering Chongqing University of Posts and Telecommunications Chongqing China Chongqing Institute of Microelectronics Industry Technology UESTC Chongqing China School of Electronic Science and Engineering University of Electronic Science and Technology of China Chengdu China

The W-band frequency range has garnered considerable attention among researchers, necessitating the development of efficient frequency doubling techniques. This paper introduces a novel W-band broadband frequency doubler employing a Schottky diode-based approach. A varactor diode, specifically the M4AE1310 model, serves as the crucial nonlinear element in the frequency doubler design. To streamline the model structure, the biased DC ground structure is eliminated. The frequency doubler comprises a waveguide-microstrip probe, a ground-matched direct, a CMRC (compact microstrip resonant cell) low-pass filter, and an input-output matching section. The modeling simulation is conducted using a combined ADS and HFSS. The simulation results demonstrate exceptional frequency doubling efficiency, yielding an output power of approximately 10 dBm when driven with a power of 20 dBm within the W-band frequency range.

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Inductive Loop Operation Versus Loop Antenna for Partial Discharge Detection

Inductive Loop Operation Versus Loop Antenna for Partial Dis...

引用

IEEE International Conference on Dielectrics (ICD)

作者： Sana Chouaibi Mohamed Hadj Said Antonino Imburgia Pietro Romano Sinda Kaziz Guido Ala Mossaad Ben Ayed Denis Flandre Fares Tounsi National Engineering School of Sousse (ENISo) Sousse University Tunisia Center for Research in Microelectronics & Nanotechnology (CRMN) Sousse Tunisia Department of Engineering L.E.PR.E.H.V. Laboratory University of Palermo Italy SMALL Group ICTEAM Institute Université catholique de Louvain Belgium

ISBN: (数字)9798350308976

ISBN: (纸本)9798350308983

This article delves into the application and efficacy of planar loop sensors for detecting partial discharge (PD) phenomena. The preference for loop sensors in PD detection stems from their simple design, non-destructive testing feature, and contactless characteristics. The paper explores both experimental and finite element modeling (FEM) approaches to evaluate the performance of distinct planar square spiral sensors in PD detection. The primary objective of the study is to compare inductive loops with loop antennas by varying the geometric parameters to achieve each approach. Two single-turn square loop antennas were designed, with a circumference of 30 cm and 75 cm, and compared with four multi-turn square inductive loops with an exterior side of 31.2 mm and varying geometric parameters. The figures of merit of all sensors, such as inductance, quality factor, and resonant frequency, are extracted through measurement and simulation to identify the most influential parameter that maximizes the sensing capability toward PD.

关键词： Q-factor Partial discharges Antenna measurements Inductance Sensitivity Magnetic sensors Loop antennas

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Hardware Implementation of Optimized LeNet-5

Hardware Implementation of Optimized LeNet-5

引用

Computational modeling, simulation and Data Analysis (CMSDA), International Conference on

作者： Junlei Ju Cheng Liu School of Microelectronics Shanghai University Shanghai China

Convolutional Neural Network (CNN), a feedforward neural network, is widely used in large-scale machine learning tasks such as image recognition, image classification, and object detection. Although CNN has strong performance, its application in daily embedded systems is limited due to the complex network hierarchy and a large amount of data. In this paper, the LeNet-5 network structure is optimized. The recognition accuracy of the optimized network on the MNIST dataset is 98.32%, but the number of weights is reduced by more than ten times compared with the LeNet-5 network, and data quantization is used to convert the weights into 8-bit fixed-point numbers, which is more suitable for deployment in the hardware with limited resources and power consumption. At the same time, different hardware structures and optimization strategies are designed for each layer of the network, and the convolution, pooling and fully connected layers are computed in parallel and optimized using methods such as loop unrolling and pipelining. Finally, the feasibility of the hardware design is verified by simulating each layer using the MNIST dataset and quantized weights.

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A simulation design of Band1 Saw Duplexer

A Simulation Design of Band1 Saw Duplexer

引用

SPAWDA Symposium on Piezoelectricity, Acoustic Waves, and Device Applications

作者： Qiu-Qun Tong Ya-Li Zou Yuan-Dong Gu School of Microelectronics Shanghai University Shanghai P. R. China Shanghai Industrial μTechnology Research Institute Shanghai P. R. China

ISBN: (纸本)9798350320817

This paper describes the design and simulation of a small volume, low insertion loss, and high isolation Band1 SAW duplexer. Compared to mainstream Band1 SAW Duplexer, for example Murata SAYEY1G95HA0F0A, our simulation results show that the design enables a package size reduction of ~25%, with the length and width shortened by 200 microns respectively. The design has a similar 1.8dB insertion loss and a superior 60dB isolation. Exacerbation of internal electromagnetic coupling on the performance caused by the reduction of package size is successfully resolved with iterative optimization of the PCB layer and main circuit structure. This compact Band1 SAW duplexer design has the potential to meet the more and more stringent size requirement of radio frequency communication in future mobile devices.

关键词： Performance evaluation Solid modeling Micrometers simulation Surface acoustic waves Insertion loss Piezoelectricity

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