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International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)

作者： Mamed R. Ismail-zade Konstantin O. Petrosyants Lev M. Sambursky Xu Zhang Bo Li Jiajun Luo Zhengsheng Han National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics) Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia Institute of Microelectronics of Chinese Academy of Sciences Beijing China

A set of modified compact SPICE models of various flavours of MOSFETs (fabricated by bulk, SOI and SOS technologies) is presented for circuit simulation in the deep-cryogenic temperature range down to 4 K, which is important for space applications and development of scalable quantum computers. All models are constructed using the approach combining macromodeling based on the standard models available in the library of SPICE models and introducing smooth analytical functions continuous with temperature for the model parameters. A unified automated procedure for model parameter extraction is presented for all the models, providing an acceptable accuracy of accounting for electrical and temperature effects for practical applications in the temperature range from room temperature to 4 K.

关键词： Semiconductor device modeling Temperature distribution Analytical models MOSFET Computational modeling Cryogenics SPICE

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A Calibration Procedure for Sensor Based Adaptive Voltage Scaling Approaches 29

A Calibration Procedure for Sensor Based Adaptive Voltage Sc...

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29th IEEE International Symposium on Power and Timing modeling, Optimization and simulation, PATMOS 2019

作者： Niemann, Christoph Ali, Munawar Heller, Jakob Timmermann, Dirk Institute of Applied Microelectronics and Computer Engineering University of Rostock Rostock Germany

ISBN: (纸本)9781728121031

Nowadays, VLSI systems suffer from increasing impacts of aging and variability. Traditionally, this is treated by applying extensive guard bands. As those guard bands are chosen at design time, they are necessarily worst case guard bands. Thus, most often they are too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based Adaptive Voltage Scaling (AVS). AVS typically relies on assumptions regarding the timing behavior of the application logic in relation to the behavior of a specific canary or sensor logic. Most published approaches use manually gained empirical data of just a few test chips and application designs for this purpose. However, to practically apply these techniques, an automatic calibration flow is needed. We propose such an automated calibration flow and test it on multiple FPGAs. We achieve an average power saving of 67%. © 2019 IEEE.

关键词： Field programmable gate arrays (FPGA)

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design and simulation of a Robust Powerline Telemetric Data Transmission System with Time Variant Voltage Surge Channel

Design and Simulation of a Robust Powerline Telemetric Data ...

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Annual Conference of Industrial Electronics Society

作者： ZHANG Hongbao Institute of Microelectronics Singapore

ISBN: (数字)9781728154145

ISBN: (纸本)9781728154152

This paper describes a design of a telemetric data transmission system for prospecting industry application. The system is for one direction data transmission, where the transmitter is mounted together with the sensors at the front of an electrical motor in the downhole under the earth surface or seabed; while the receiver is mounted at the ground. The transmitter is coupled to the power line driving the motor, and the length of the power line ranges from several hundred meters to few kilometers. The design challenges are: limited available bandwidth with big variations on channel response, omni background noise, coupled with several clusters of time variant in-band interference tones which are much stronger than the desired signal. The simulation result shows that the designed system can achieve a data rate of 200 b/s over the bandwidth less than 5.2 KHz with two tone interferences that 40 dB higher than the signal.

关键词： Interference Frequency diversity Transmitters Sensors Receivers Integrated circuit modeling Data models

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Electrothermal modeling of GaN Power Transistor for High Frequency Power Converter design

Electrothermal Modeling of GaN Power Transistor for High Fre...

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European Conference on Power Electronics and Applications

作者： Loris Pace Florian Chevalier Arnaud Videt Nicolas Defrance Nadir Idir Jean-Claude De Jaeger LABORATORY OF ELECTRICAL ENGINEERING AND POWER ELECTRONICS University of Lille Avenue Henri Poincaré Cité Scientifique Villeneuve d’ Ascq France INSTITUTE OF ELECTRONICS MICROELECTRONICS AND NANOTECHNOLOGIES University of Lille Avenue Henri Poincaré Cité Scientifique Villeneuve d’ Ascq France

ISBN: (数字)9789075815368

ISBN: (纸本)9781728198071

This work proposes the electrothermal modeling of a packaged GaN power transistor in order to evaluate by simulation its performances in a 200 W - 1 MHz DC/DC converter. The complete electrical modeling of the high frequency converter using EM-circuit co-simulations is presented. After validation of the GaN transistor switchings waveforms and estimation of power losses, the operating temperature of the device is simulated and experimentally validated.

关键词： Gallium nitride Transistors Transmission line measurements Schottky diodes Scattering parameters Capacitance

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A Robust Exponential Integrator Method for Generic Nonlinear Circuit simulation

A Robust Exponential Integrator Method for Generic Nonlinear...

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design Automation Conference

作者： Quan CHEN Engineering Research Center of Integrated Circuits for Next-Generation Communications Ministry of Education School of Microelectronics Southern University of Science and Technology Shen Zhen China

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

In this paper, we aim to address two long-lasting issues in large scale transient circuit simulation using the exponential integrator (EI) method. First is the numerical instability caused by the singularity in the differential-algebraic equation system. Our proposed solution is a systematic, algebraic and sparsity preserving regularization technique to eliminate the unstable modes in the system to be solved. Next, we devise a generic scheme to apply Newton-Raphson iterations in the EI framework for enhanced nonlinearity handling capability. With the two techniques, we wish to elevate the robustness and performance of EI and make it a competitive alternative to the existing SPICE-type simulators in practical usage.

关键词： Nonlinear circuits Integrated circuit modeling Linear systems Jacobian matrices Transient analysis Mathematical model Linear circuits

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From Silicon to simulation: A Full Decomposition of a Fabricated 130 nm Serial Peripheral Interface for Establishing an Assurance Baseline Root-of-Trust

From Silicon to Simulation: A Full Decomposition of a Fabric...

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Physical Assurance and Inspection of Electronics (PAINE), 2020 IEEE

作者： Adam G. Kimura Adam R. Waite Jon Scholl James Schaffranek Matt Sutter Glen D. Via Battelle Memorial Institute Cyber Trust & Analytics Columbus OH Air Force Research Labs ARFL/RYDT OH

ISBN: (数字)9781728161211

ISBN: (纸本)9781728161228

This paper reviews the decomposition of a fabricated Serial Peripheral Interface (SPI) that was manufactured in a 130 nm process node technology to establish a verification and validation methodology for baselining microelectronics assurance. The fabricated SPI goes through a delayering process where each target layer is captured and imaged using a Raith 150 Chipscanner. The features for each layer are extracted allowing a GDSII layout file to be generated and subsequent design netlist to be recovered. The extracted GDSII was compared to the original reference GDSII, exposing additional fill cells that were added to the design at the foundry. The recovered netlist was validated as logically equivalent to the original golden design netlist and was simulated in the original verification testbench, passing 100% of the original model checks. By passing the GDSII comparison, functional model checks, and logical equivalence checks, the fabricated SPI was determined to be trusted. A methodology for establishing an assurance baseline root-of-trust has been proven.

关键词： SRAM chips Layout Inspection Feature extraction Silicon microelectronics Integrated circuit modeling

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Post-Route Performance Estimation Method for Reconfigurable Systems-on-a-Chip

Post-Route Performance Estimation Method for Reconfigurable ...

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IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Sergey V. Gavrilov Vasilii M. Khvatov Daniil A. Zheleznikov Tatiana V. Garbulina Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

ISBN: (数字)9781728157610

ISBN: (纸本)9781728157627

The well-known methods for evaluating the performance of digital circuits designed using the Field-Programmable Gate Array (FPGA) or Reconfigurable System on a Chip (RSoC) use simplified elements delay model or the simulation of the final post-routing SPICE-netlist. SPICE simulation is highly dependent on the circuit size and the amount of used routing resources and can be time-consuming. Therefore, it's necessary to quickly evaluate the circuit performance before the verification stage using SPICE simulation. Performance evaluation is required after routing as well as at the other design *** article describes the developed method for the quick post-routing performance estimation. We show its necessity and present a step-by-step process of adding it in a whole RSoC design flow. This method uses software that performs static timing analysis using a characterized logic elements library in Liberty format and nets capacitive characteristics. The article also considers the advantages, limitations, problems and features of the proposed method.

关键词： Capacitance Delays Routing Integrated circuit modeling Field programmable gate arrays Libraries

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design Guidelines of Magnetic Tunnel Junctions with Two-dimensional Tunneling Barrier Layer: Atomistic simulation Study from Material to Device

Design Guidelines of Magnetic Tunnel Junctions with Two-dime...

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International Electron Devices Meeting (IEDM)

作者： Xiaolei Ma Jiezhi Chen Kaiyou Wang Runsheng Wang Ru Huang Institute of Microelectronics Peking University Beijing China State Key Laboratory of Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences Beijing China School of Information Science and Engineering Shandong University Qingdao China

ISBN: (纸本)9781665425735

Based on density functional theory (DFT) and non-equilibrium Green's function (NEGF) formalism, the magnetic tunnel junctions (MTJs) with 2D tunneling barrier (TB) material are systematically simulated from the material level to the device level. The magnetic properties of ferromagnetic metal (FM), spin-orbit coupling (SOC) of 2D TB, tunneling magnetoresistance (TMR) and I-V characteristics of MTJs are thoroughly studied. The effects of TB doping and interfacial layer (IL) engineering are discussed. We pointed out for the first time that 2D FM Fe 3 FeTe 2 (FGT) and 2D semiconductors contacts can form good $n$ -type contacts with lower Schottky barrier (SBH), especially the SBH is almost zero in FGT-InSe interface. More importantly, for the first time, it is found that each layer of FGT shows obvious perpendicular magnetic anisotropy (PMA) in FGT|WSe 2 |FGT MTJ, which means that each layer of FGT used in MTJs contributes to the total MAE. On the other hand, MTJs using FGT can effectively suppress the minority-spin-transport channel and thus significantly improve TMR. In addition, graphene IL, TB doping and different TB layers are examined to further modulate TMR.

关键词： Schottky barriers Two dimensional displays Metals Doping Tunneling magnetoresistance Semiconductor process modeling Perpendicular magnetic anisotropy

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电流模BUCK DC-DC变换器的系统建模与仿真

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电子与封装 2022年第9期22卷 48-54页

作者：王聪刘颖异唐旭升东南大学微电子学院江苏无锡214000 东南大学网络空间安全学院南京211102

开关电源转换器是一个闭环网络控制系统,此系统存在高阶、离散、非线性和时变等特性。提出了一个连续导通模式(CCM)下脉冲宽度调制(PWM)控制的电流模BUCK变换器的小信号模型,该模型描述了系统稳态工作时的小信号特性。通过集成电路设计... 详细信息

开关电源转换器是一个闭环网络控制系统,此系统存在高阶、离散、非线性和时变等特性。提出了一个连续导通模式(CCM)下脉冲宽度调制(PWM)控制的电流模BUCK变换器的小信号模型,该模型描述了系统稳态工作时的小信号特性。通过集成电路设计工具Virtuoso,利用AnalogLib库中的理想器件得到关于近似函数的小信号模型。通过对小信号模型的稳定性仿真,能够预测电流模式控制的电源变换器的所有小信号特性,包括BUCK次谐波振荡的产生、斜坡补偿和补偿网络对系统稳定性的影响。

关键词： DC-DC变换器脉冲宽度调制系统建模斜坡补偿电源管理

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Quasi-3D Thermal simulation of Multi-Chip Stack Embedding Package

Quasi-3D Thermal Simulation of Multi-Chip Stack Embedding Pa...

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International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)

作者： Konstantin O. Petrosyants Nikita I. Ryabov Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russian Federation National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics) Moscow Russian Federation

Multi-chip embedded PCBs were in resent years the mainstream technology of electronic packaging size reduction and at the same time providing improved performance. Ultra-small package size obviously strongly impacts the SiP module thermal behaviour. Unfortunately the complete thermal design methodology was not developed for this technology till now. In this work the problem of thermal design is completely solved using quasi-3D approach taking into account the main features of embedded PCB constructions: 1) 3D integration of ICs and board; 2) a large number of thinned layers of different materials; 3) vertical z-axis interconnections through the package layers. A ten times decrease of central processing unit (CPU) time is achieved as compared with the full 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature T MAX determination for different types of packages is not more than 10-20%.

关键词： Heating systems Solid modeling Temperature distribution Three-dimensional displays Computational modeling Electronic packaging thermal management Numerical models

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