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Investigations on Cylindrical Surrounding Double-gate (CSDG) Mosfet using ALXGA1-XAS/INP: PT with LA2O3 Oxide Layer for Fabrication

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RECENT PATENTS ON NANOTECHNOLOGY 2024年第3期18卷 374-385页

作者： Gowthaman, Naveenbalaji Srivastava, Viranjay M. Univ KwaZulu Natal Dept Elect Engn ZA-4041 Durban South Africa

Background/Introduction: The Cylindrical Surrounding Double-Gate MOSFET has been designed using Aluminium Gallium Arsenide in its arbitrary alloy form alongside Indium Phosphide with Lanthanum Dioxide as a high-kappa dielectric material. Objective: To conduct research on the novel application of AlxGa1-xAs/InP: Pt with La2O3 oxide layer in the fabrication of Cylindrical Surrounding Double-gate (CSDG) MOSFET, with the ultimate goal of obtaining patentable findings and developing intellectual property in the field. The heterostructure based on the AlxGa1-xAs/InP: Pt has been used in the design and implementation of the MOSFET for RF applications. Platinum serves as the gate material, which has higher electronic immunity toward the Short Channel Effect and highlights semiconductor properties. The charge buildup is the main concern in the field of MOSFET design when two different materials are considered for fabrication. Methods: The usage of 2 Dimensional Electron Gas has been outstanding in recent years to help the electron buildup and charge carrier accumulation in the MOSFETs regime. Device simulation used for the smart integral systems is an electronic simulator that uses the physical robustness and the mathematical modeling of semiconductor heterostructures. In this research work, the fabrication method of Cylindrical Surrounding Double Gate MOSFET has been discussed and realized. The scaling down of the devices is essential to reduce the area of the chip and heat generation. By using these cylindrical structures, the area of contact with the circuit platform is reduced since the cylinder can be laid down horizontally. Results: The coulomb scattering rate is observed to be 18.3% lower than the drain terminal when compared to the source terminal. Also, at x = 0.125 nm, the rate is 23.9%, which makes it the lowest along the length of the channel;at x = 1 nm, the rate is 1.4% lesser than that of the drain terminal. A 1.4 A/mm(2) high current density had been achieved

关键词： Arbitrary alloys high-kappa dielectrics microelectronics nanomaterials semiconductors low power/energy CSDG MOSFET VLSI

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Analysis and modeling of System Performance Based on Random Matching Errors, Gradient Errors, and Finite Output Impedance of Current-source DAC 3

Analysis and Modeling of System Performance Based on Random ...

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2023 3rd International Conference on Electronics, Circuits and Information Engineering, ECIE 2023

作者： Ma, Zhihua Song, Zheng Yao, Yao Hu, Jianguo School of Microelectronics Science and Technology Sun Yat-sen University Guangdong Province Zhuhai519000 China Shenzhen Research Institute Sun Yat-Sen University Guangdong Province Shenzhen518000 China Development Research Institute of Guangzhou Smart City Guangdong Province Guangzhou510000 China

With the development of communication technology, the performance of digital-to-analog converters as the last link in signal processing is particularly important. This paper analyzes the errors of current rudder DAC and their effect on DAC performance. Different compensation methods are proposed to compensate for or eliminate the errors. Through system modeling, it is concluded that under the conditions of static parameters DNL90dB and SNDR>70dB, the random matching error should be less than 0.001, the gradient error less than 1E-5 and the admittance rate less than 1E-7. The correctness of the theoretical analysis can be verified through system modeling and simulation, providing accurate guidance direction for circuit design and greatly shortening the design cycle. © Published under licence by IOP Publishing Ltd.

关键词： Digital to analog conversion

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simulation Analysis Thermal Damage Effect of Strong Electromagnetic Pulse on PIN Limiter

Simulation Analysis Thermal Damage Effect of Strong Electrom...

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2023 Cross Strait Radio Science and Wireless Technology Conference, CSRSWTC 2023

作者： Bing, Ruan Dongdong, Wang Wenzhuo, Wang Shengquan, Zheng Xujing, Huang Science and Technology on Electromagnetic Compatibility Laboratory Wuhan430064 China China Ship Development and Design Center Wuhan430064 China

The effects of pulse power and rise time on the performance of PIN limiter and internal temperature of PIN diode have been analyzed through multi-physics modeling simulation. The results show that the leakage power of... 详细信息

ISBN: (纸本)9798350358971

关键词： PIN Limiter Strong Electromagnetic Pulse Thermal Damage Effect

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First large-scale (68×25×5 nm3) atomistic modeling for accurate and efficient etching process based on machine learning molecular dynamics (MLMD)

First large-scale (68×25×5 nm3) atomistic modeling for acc...

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2024 IEEE International Electron Devices Meeting, IEDM 2024

作者： Feng, Zemeng Hu, Ziyi Yu, Tong Lai, Panpan Ge, Rui Shao, Hua Shang, Dashan Li, Zhiqiang Xu, Kui Li, Junjie Chen, Rui Li, Ling State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9798350365429

Revealing the reaction mechanisms in manufacturing advanced devices is crucial for enhancing performance at nodes below 3 nm. In this study, we introduce the first large-scale atomistic model utilizing a machine learning molecular dynamics (MLMD) framework. This model simulates the lateral isotropic selective etching process of SiO2/Si stack structures in Gate-all-around field-effect transistors (GAAFETs) using F* radical plasma. The dataset for this model is generated using active learning strategies based on search for F* radical reacting with Si(100) substrate. Our simulation spans 68×25×5 nm3, involving over 600,000 atoms, and demonstrates a 4× improvement in model error for etching reaction trends compared to the classic molecular dynamics (CMD) method. Additionally, the model achieves a typical runtime of 16.7 hours, representing a ~44.9× speedup over CMD. Moreover, the simulation provides detailed reaction path and uncovers the mechanisms behind lateral etching. This framework paves the way for potential atom-to-device multiscale process modeling, contributing to design Technology Co-optimization (DTCO). © 2024 IEEE.

关键词： Gallium arsenide

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modeling the Thermal Characteristics of Stacked 2T0C Memory Array Based on InGaZnO4 Thin-film Transistors

Modeling the Thermal Characteristics of Stacked 2T0C Memory ...

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International Conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： He, Song Li, Haoxin Xu, Guangwei Tang, Xinyi Li, Yuanbiao Kim, Jaewoo Gu, Tingting Xue, Xingkun Li, Zelun Xu, Handong Dong, Haiyang Zhou, Kai Hu, Xianqin Long, Shibing Univ Sci & Technol China Sch Microelect Hefei 230026 Peoples R China Changxin Memory Technol Inc Hefei 230601 Peoples R China

ISBN: (纸本)9784863488038

For the first time, the electrothermal characteristics of the stacked 2T0C memory array were modeled based on the material properties, electron transport mechanism of InGaZnO4 (IGZO) and basic Fourier heat flow equation utilizing the technology computer-aided design (TCAD) tool. According to the proposed electrothermal model, the multi-layer stacked 2T0C memory array would bring severe self-heating issue from the thermal crosstalk among layers. The temperature rising of stacked 2T0C cells decrease the retention time severely due to the temperature instability of IGZO thin-film transistors TFTs. Furthermore, several advanced device-level strategies were proposed to ameliorate the heat accumulation problem.

关键词： IGZO 2T0C DRAM stacked memory array self-heating TCAD simulation

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String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

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microelectronics JOURNAL 2024年 153卷

作者： Cho, Sunghwan Choi, Byoungdeog Sungkyunkwan Univ Dept Semicond & Display Engn Suwon 16419 South Korea Samsung Elect Co Memory Business Hwasung 18448 South Korea Sungkyunkwan Univ Dept Elect & Comp Engn Suwon 16419 South Korea

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

关键词： 3D charge trapping flash (CTF) memory String-level compact model Erase operation Framework Circuit simulation

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A Highly Collaborative EDA Toolset for design Technology Co-Optimization Towards Analog and Mixed Signal Circuits

A Highly Collaborative EDA Toolset for Design Technology Co-...

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2023 International Symposium of Electronics design Automation, ISEDA 2023

作者： Shao, Yali Chen, Yanning Shen, Meigen Zhang, Dong Xie, Yaoming Li, Dongmei Liang, Yingzong Chi, Boming Liu, Fang Zhao, Dongyan Meng, Qingmeng Chang, Zezhou Beijing Smart-Chip Microelectronics Technology Co. Ltd Beijing China State Grid Shanxi Electric Power Research Institute Shanxi China

ISBN: (纸本)9798350304510

In order to meet the high performance and reliability requirements of industrial chips, especially analog and mixed-signal (AMS) circuits, the process technology and circuits design need to be highly collaborative. In this paper, a design technology co-optimization (DTCO) simulation toolset is developed. It includes two parts: process technology tool and circuit design tool. The first part, process technology tool, includes high precision TCAD device simulation and testkey layout autogeneration tool. For TCAD simulation, especially LDMOS that based on drift-diffusion models, a particular hexahedral mesh was used to lower mesh complexity and improve numerical accuracy. This tool can accurately calculate key electrical parameters such as Rdson, BVoff, Vth, BVon, etc. The automatic layout generator tool was used to generate the testkey layout for WAT testing, device modeling and reliability testing etc. The second part, circuit design tool, consists of unified automatic signal sampling scheme for XPS/Cosim verification, making finally packaged real number;Different quick waveform storage method to accelerate results check;and whole chip over-voltage (OV)/forward diodes check for customized process. This DTCO simulation toolset is verified by a power management chip PMIC620 which includes analog and mixed signal circuits, based on the 0.18um 40V BCD technology. The chip is tapeout with first silicon successful. © 2023 IEEE.

关键词： Timing circuits

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Harmonic Transfer Function modeling of LCC-S Inductive Power Transfer System

Harmonic Transfer Function Modeling of LCC-S Inductive Power...

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2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023

作者： Gong, Cheng Ding, Zhaoyi Lam, Chi-Seng University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China University of Macau Institute of Microelectronics China University of Macau Faculty of Science and Technology Department of Electrical and Computer Engineering China

ISBN: (纸本)9798350316445

Mathematical model of the inductive power transfer (IPT) systems is essential for stability analysis and control design. Conventional modeling approaches for IPT systems result in high-order models, as each resonant voltage or current is represented by two slowly changing real-valued variables. Alternative modeling methods may decrease the model order, but they are often plagued by drawbacks such as the absence of analytical expressions, reduced generality, and incomplete modeling. Moreover, the harmonic AC components of the IPT system are not well modeled in the existing methods, which affects the analysis accuracy and control optimality. In this paper, a harmonic transfer function (HTF) modeling of the IPT system is proposed, which has good mathematical properties and improved accuracy. First, the circuit configuration and the linear time-varying (LTV) large-signal model are proposed. Then, the derivation of the proposed HTF is comprehensively discussed. Finally, the accuracy of the proposed HTF is verified by simulation and experimental results in comparison with other representative modeling methods, which shows an improved accuracy. © 2023 IEEE.

关键词： harmonics transfer function inductive power transfer system modeling

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Investigation of Parasitic Background IR Radiation Levels on a Photodetector Surface in a Vacuum Cryostat

Investigation of Parasitic Background IR Radiation Levels on...

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2022 IEEE International Multi-Conference on Engineering, Computer and Information Sciences, SIBIRCON 2022

作者： Novoselov, Andrew R. Dobrovolsky, Peters P. Khryashchev, Sergey V. Shatunov, Konstantin P. Aldokhin, Pavel A. Dept. of Thermal Imaging and Television Technology and Design Institute of Applied Microelectronics Novosibirsk Branch of Rzhanov Institute of Semiconductor Physics Siberian Branch of the Russian Academy of Sciences Novosibirsk Russia Dept. of Modeling of Electrooptical Devices Novosibirsk Branch of Rzhanov Institute of Semiconductor Physics Siberian Branch of the Russian Academy of Sciences Technology and Design Institute of Applied Microelectronics Novosibirsk Russia

ISBN: (纸本)9781665464802

The results of experimental and numerical simulations studying the stray background levels on an IR photodetector surface in a vacuum cryostat with a cylindrical diaphragm are presented in the article. The stray background value was investigated by the direct measurement with a second thermal camera pointed at the surface of the first camera's hybrid assembly. The limitations of the experimental method are the accuracy of measuring the background level on the surface of the photodetector. It is necessary to use a cooled second thermal camera as a measuring instrument since if the temperature of the photodetector in it is higher than the temperature of studied surface, and its radiation reflected from the IR photodetector does not allow reliable results to be obtained. This method of the research makes it possible to identify technological imperfections in the design of the studied cryostats. Numerical simulation makes it possible to optimize the shape and the design of cold diaphragms, but it does not allow to analyze the contributions of various sources of parasitic radiation in the cryostat. This requires additional modeling and simulation. © 2022 IEEE.

关键词： Infrared radiation

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Advanced process library irradiation parameter modeling and analysis techniques 2

Advanced process library irradiation parameter modeling and ...

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2nd International Conference on Electronic Information Technology, EIT 2023

作者： Shi, Fayin Wang, Liang Sang, Qianqian Shen, Mengdong Li, Yong Liu, Chang National University of Defense Technology Hunan Changsha410073 China Beijing Microelectronics Technology Institute Beijing100076 China

ISBN: (数字)9781510666627

ISBN: (纸本)9781510666610

The irradiation experimental analysis of chips can obtain irradiation data of advanced processes, which is beneficial to guide the research of new generation of anti-irradiation chips. In this paper, based on the GDS layout of the advanced process library, we firstly design the GDS layout hierarchy information extraction technology and implement the standard cell TCAD model automatic generation technology, then design the algorithm to generate irradiation parameters for heavy ion bombardment simulation experiments, and finally analyze the experimental data to establish the irradiation database. The experimental results show that it is feasible to establish an automatic irradiation data acquisition scheme based on the GDS layout of the advanced process library. © 2023 SPIE.

关键词： Ion bombardment

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