This paper proposes a calculation methodology for assessing the parasitic inductance within an IC package. As a case study, the BCD technology of one of the top IC suppliers was used. The results will be evaluated aga...
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ISBN:
(数字)9798350393002
ISBN:
(纸本)9798350393019
This paper proposes a calculation methodology for assessing the parasitic inductance within an IC package. As a case study, the BCD technology of one of the top IC suppliers was used. The results will be evaluated against FEM calculations in a well vetted commercial software.
The developed method in this paper presents an analytical approach for combined modeling of rising and falling transition edges to estimate jitter using an eye diagram in the presence of ground bounce noise (GBN) in a...
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ISBN:
(数字)9798331543259
ISBN:
(纸本)9798331543266
The developed method in this paper presents an analytical approach for combined modeling of rising and falling transition edges to estimate jitter using an eye diagram in the presence of ground bounce noise (GBN) in a CMOS inverter circuit. Analytical expressions are derived for all operational regions of the inverter transistors and varying input waveform slopes, establishing a comprehensive input-output relationship. The proposed model is validated through practical case studies for jitter estimation, specifically focusing on rising transition edges, and is further employed to model the eye diagram. The methodology is verified using 40 nm technology nodes from United microelectronics Corporation (UMC), demonstrating strong correlation with simulation results.
The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this ...
The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this backdrop, machine learning technologies emerge as dynamic tools for correlation building and classification, revolutionizing the traditional approaches to design, manufacturing, and testing in electronic packaging, as well as the design for Reliability (DfR) *** paper reviews the most recent AI-assisted approach for electronic packaging and then focuses on the AI-assisted DfR (AI-DfR) approaches. Our examination reveals that AI methods have been adapted to meet the specific needs of electronic packaging. The industry’s anticipation for AI-DfR stems from its potential to address prevailing reliability design challenges, yet its multidisciplinary essence poses hurdles to swift progress. This review proposes future directions for AI-DfR’s development, spotlighting critical areas such as the quality and efficiency of finite element modeling, design and optimization of training models, selection of AI models, and maintenance and value enhancement strategies.
As Network on chip (NoC) architecture de-velops as an solution of interconnection in System on chip (SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation frame-wor...
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As Network on chip (NoC) architecture de-velops as an solution of interconnection in System on chip (SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation frame-work becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification plat-form. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simu-lation speed, and lower step to relative development of software. The experimental results show that the mixed-level NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.
In this work, we first fitted the three different Fe tailing effects (slopes) with the corresponding two-dimensional electron gas (2DEG) concentration and mobility based on experimental data, obtaining the correspondi...
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The present study designs and implements a microelectromechanical system (MEMS) capacitive microphone with a ribbed backplate for improving the reliability performance in the high pressure burst test (HPBT). During th...
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This paper presents the software coupling of an analog circuit simulator (ACS) to a machine learning (ML) execution engine, in order to enable usage of ML models in circuit simulation context. This is achieved by inte...
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In the development cycle of microelectronic components and systems, comprehensive reliability assessments of the products in the virtual environment save the costs of manufacturing prototypes. In this simulation proce...
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ISBN:
(数字)9798350393002
ISBN:
(纸本)9798350393019
In the development cycle of microelectronic components and systems, comprehensive reliability assessments of the products in the virtual environment save the costs of manufacturing prototypes. In this simulation process, component manufacturers need to share component models with other partners along the value chain while at the same time safeguarding their intellectual property. Therefore, in this work, model order reduction methods are implemented to generate highly accurate compact models, which hide the details of the product, such as material properties and geometry. For system manufacturers, that integrate different components on a printed circuit board, these compact models can be re-integrated into their models for virtual reliability tests via the superelement techniques.
The open-circuit voltage is a crucial parameter that determines the harvesting capabilities of diodes operating in the photovoltaic regime. It is highly dependent on temperature and illumination which may limit the di...
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ISBN:
(数字)9798350351927
ISBN:
(纸本)9798350351934
The open-circuit voltage is a crucial parameter that determines the harvesting capabilities of diodes operating in the photovoltaic regime. It is highly dependent on temperature and illumination which may limit the diode operation in application scenarios with large temperature and illumination variations as space instrumentation. The former dependence has not been modeled in a Hardware Description Language. This work presents a Verilog-A/MS based compact model to study and simulate the phenomenon. Validation of the model was conducted through TCAD simulations across a broad operational spectrum. The results affirm the model’s capability to analyze the impact of temperature fluctuations on solar cell performance accurately.
As the geometries of transistors continue to scale down, single-event transient (SET) are becoming a major source of soft errors in circuit design. This paper proposes a machine learning method for modeling SET in cir...
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