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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Ștefan Ardeleanu Ioan Marius Purcar Cristian Boianceanu Electrotechnics and Measurements Department Technical University of Cluj-Napoca Cluj-Napoca Romania Design Enabling Services Infineon Technologies Romania Bucharest Romania

This paper proposes a calculation methodology for assessing the parasitic inductance within an IC package. As a case study, the BCD technology of one of the top IC suppliers was used. The results will be evaluated aga... 详细信息

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

关键词： Micromechanical devices Inductance Metallization Conductors Reliability engineering Software Finite element analysis microelectronics Transistors Optimization

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modeling of Eye Diagram for Jitter Estimation in Presence of Ground Bounce

Modeling of Eye Diagram for Jitter Estimation in Presence of...

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Electrical design of Advanced Packaging and Systems Symposium, EDAPS

作者： Anuj Kumar Jai Narayan Tripathi Indian Institute of Technology Jodhpur

ISBN: (数字)9798331543259

ISBN: (纸本)9798331543266

The developed method in this paper presents an analytical approach for combined modeling of rising and falling transition edges to estimate jitter using an eye diagram in the presence of ground bounce noise (GBN) in a CMOS inverter circuit. Analytical expressions are derived for all operational regions of the inverter transistors and varying input waveform slopes, establishing a comprehensive input-output relationship. The proposed model is validated through practical case studies for jitter estimation, specifically focusing on rising transition edges, and is further employed to model the eye diagram. The methodology is verified using 40 nm technology nodes from United microelectronics Corporation (UMC), demonstrating strong correlation with simulation results.

关键词： Semiconductor device modeling Analytical models simulation Focusing Estimation Jitter Inverters Data models Transistors Integrated circuit modeling

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AI-assisted design for Reliability: Review and Perspectives

AI-assisted Design for Reliability: Review and Perspectives

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Cadmus Yuan S. D. M de Jong Willem D. van Driel Department of Mechanical and Computer-aided Engineering Feng Chia University Taichung Taiwan No. 100 Wenhwa Rd. Seatwen Taichung Taiwan R.O.C Department of Microelectronics Delft University of Technology Delft Netherlands Mekelweg 4 2628 CD Delft Netherlands

The demand for rapid advancement in AI, mobile and automotive markets is pushing the boundaries of electronic packaging, including heterogeneous integration, high-power packages, and large-die packaging. Against this backdrop, machine learning technologies emerge as dynamic tools for correlation building and classification, revolutionizing the traditional approaches to design, manufacturing, and testing in electronic packaging, as well as the design for Reliability (DfR) *** paper reviews the most recent AI-assisted approach for electronic packaging and then focuses on the AI-assisted DfR (AI-DfR) approaches. Our examination reveals that AI methods have been adapted to meet the specific needs of electronic packaging. The industry’s anticipation for AI-DfR stems from its potential to address prevailing reliability design challenges, yet its multidisciplinary essence poses hurdles to swift progress. This review proposes future directions for AI-DfR’s development, spotlighting critical areas such as the quality and efficiency of finite element modeling, design and optimization of training models, selection of AI models, and maintenance and value enhancement strategies.

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Mixed-Level modeling Methodology for Network-on-Chip Architecture Exploration

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Chinese Journal of Electronics 2025年第3期23卷 468-473页

作者： Shouyi Yin Zhen Zhang Yang Hu Leibo Liu Shaojun Wei Institute of Microelectronics Tsinghua University Beijing China National Laboratory for Information Science and Technology Tsinghua University Beijing China

As Network on chip (NoC) architecture de-velops as an solution of interconnection in System on chip (SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation frame-work becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification plat-form. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simu-lation speed, and lower step to relative development of software. The experimental results show that the mixed-level NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.

关键词： Performance evaluation Analytical models Accuracy Multiprocessor interconnection Network-on-chip Software Hardware Space exploration System-level design

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TCAD modeling, Validation, and Performance Prediction of Fe Tail Effects in AlGaN/GaN HEMTs Based on Experimental Data 21

TCAD Modeling, Validation, and Performance Prediction of Fe ...

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21st China International Forum on Solid State Lighting and 10th International Forum on Wide Bandgap Semiconductors, SSLCHINA: IFWS 2024

作者： Su, Xuan Yang, Ling Gao, Wenze Lu, Hao School of Microelectronics Xidian University Xi’an710071 China

ISBN: (纸本)9798331541149

In this work, we first fitted the three different Fe tailing effects (slopes) with the corresponding two-dimensional electron gas (2DEG) concentration and mobility based on experimental data, obtaining the corresponding 2DEG concentrations and mobilities under different Fe tailing effects. Subsequently, we established a Silvaco TCAD simulation model for AlGaN/GaN HEMTs based on the three Fe tailing effects and validated the model's accuracy using experimental data. Finally, the model was used to predict the impact of an additional Fe tailing effect on the performance of AlGaN/GaN HEMTs. This approach provides a strong reference for the design of epitaxial structures utilizing Fe-doped buffer layers. ©2024 IEEE.

关键词： Aluminum gallium nitride

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A MEMS CAPACITIVE MICROPHONE WITH RIBBED BACK-PLATE FOR ENHANCING HIGH-PRESSURE RELIABILITY PERFORMANCE 29

A MEMS CAPACITIVE MICROPHONE WITH RIBBED BACK-PLATE FOR ENHA...

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29th International Congress on Sound and Vibration, ICSV 2023

作者： Peng, Tzu-Huan Hsu, Huei-Ju Huang, Jin H. Huang, Chien-Hsing Feng Chia University Taichung Taiwan Qsensing Microelectronics Co. Ltd.

ISBN: (纸本)9788011034238

The present study designs and implements a microelectromechanical system (MEMS) capacitive microphone with a ribbed backplate for improving the reliability performance in the high pressure burst test (HPBT). During the fabrication process as the anti-stick dimples, the ribs are patterned in the vicinity of the vent holes in the peripheral region of the backplate. The backplate with various vent hole size and ribbing range are investigated to enable us to choose proper design. Finite element method (FEM) and lumped parameter circuit modeling approaches are proposed to validate physical testing. Both the simulation and experimental results indicate that the ribbed backplate greatly improves the reliability performance in HPBT compared to the unribbed backplate, but at the expense of a small amount of signal-to-noise ratio. © 2023 Proceedings of the International Congress on Sound and Vibration. All rights reserved.

关键词： Reliability

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Machine learning in the analog circuit simulation loop 16

Machine learning in the analog circuit simulation loop

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2021 International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th Conference on PhD Research in microelectronics and Electronics, PRIME 2021

作者： Tzenov, Petar Sokar, Ahmed Infineon Technologies AG Neubiberg Germany

ISBN: (纸本)9783800755899

This paper presents the software coupling of an analog circuit simulator (ACS) to a machine learning (ML) execution engine, in order to enable usage of ML models in circuit simulation context. This is achieved by interfacing Infineon’s in-house simulator, TITAN, with the widely accepted machine learning framework TensorFlow (TF), via an easy to use Verilog-A API. Here we introduce the basic characteristics of this interface and present an application example for its usage in analog circuit behavioral modeling. © VDE VERLAG GMBH.

关键词： Analog circuits

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Reduced-Order Modelling for Efficient Chip-Package-Board design

Reduced-Order Modelling for Efficient Chip-Package-Board Des...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Chengdong Yuan Sönke Maeter Simon Kuttler Olaf Wittler Tamara Bechtold Jade University of Applied Sciences Wilhelmshaven Germany Cadfem GmbH Munich Germany Fraunhofer IZM Berlin Germany

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

In the development cycle of microelectronic components and systems, comprehensive reliability assessments of the products in the virtual environment save the costs of manufacturing prototypes. In this simulation process, component manufacturers need to share component models with other partners along the value chain while at the same time safeguarding their intellectual property. Therefore, in this work, model order reduction methods are implemented to generate highly accurate compact models, which hide the details of the product, such as material properties and geometry. For system manufacturers, that integrate different components on a printed circuit board, these compact models can be re-integrated into their models for virtual reliability tests via the superelement techniques.

关键词： Micromechanical devices Printed circuits Virtual environments Prototypes Intellectual property microelectronics Manufacturing Integrated circuit modeling Integrated circuit reliability Material properties

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A Verilog-A/MS Compact Model for the Temperature Dependency of the Open-Circuit Voltage for Integrated Diodes

A Verilog-A/MS Compact Model for the Temperature Dependency ...

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International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： Pablo Fernández-Peramo Juan A. Leñero-Bardallo Sergio Palomeque-Mangut Ángel Rodríguez-Vázquez Institute of Microelectronics of Seville (IMSE-CNM) CSIC-Universidad de Sevilla Spain

ISBN: (数字)9798350351927

ISBN: (纸本)9798350351934

The open-circuit voltage is a crucial parameter that determines the harvesting capabilities of diodes operating in the photovoltaic regime. It is highly dependent on temperature and illumination which may limit the diode operation in application scenarios with large temperature and illumination variations as space instrumentation. The former dependence has not been modeled in a Hardware Description Language. This work presents a Verilog-A/MS based compact model to study and simulate the phenomenon. Validation of the model was conducted through TCAD simulations across a broad operational spectrum. The results affirm the model’s capability to analyze the impact of temperature fluctuations on solar cell performance accurately.

关键词： Semiconductor device modeling Photovoltaic systems Analytical models Temperature dependence Temperature distribution Photovoltaic cells Instruments Lighting Integrated circuit modeling Hardware design languages

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Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level simulation 15

Machine Learning-Assisted Single-Event Transient Model of 12...

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15th IEEE International Conference on ASIC, ASICON 2023

作者： Lin, Jianwen Cai, Linlin Chen, Yutao Zhang, Haoyu Chen, Wangyong Sun Yat-sen University School of Microelectronics Science and Technology Guangzhou510275 China Sun Yat-sen University Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Guangzhou510275 China

ISBN: (纸本)9798350312980

As the geometries of transistors continue to scale down, single-event transient (SET) are becoming a major source of soft errors in circuit design. This paper proposes a machine learning method for modeling SET in circuit-level simulations with the high efficiency, since traditional models such as the double exponential model are not coupled with circuit responses. The proposed artificial neural network (ANN) model shows a great prediction accuracy for single-event transient currents in 12nm FinFET technology under different time, linear energy transfer (LET), bias voltage, and strike positions. The trained model can be implemented into SPICE with Verilog-A for circuit-level simulation, and its validity in a 7-stage inverter chain and a 6T SRAM are demonstrated to provide the rapid guidance for radiation reliability. © 2023 IEEE.

关键词： FinFET machine learning neural network Single-event transient

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