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15th IEEE International Conference on ASIC, ASICON 2023

作者： Lin, Jianwen Cai, Linlin Chen, Yutao Zhang, Haoyu Chen, Wangyong Sun Yat-sen University School of Microelectronics Science and Technology Guangzhou510275 China Sun Yat-sen University Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Guangzhou510275 China

ISBN: (纸本)9798350312980

As the geometries of transistors continue to scale down, single-event transient (SET) are becoming a major source of soft errors in circuit design. This paper proposes a machine learning method for modeling SET in circuit-level simulations with the high efficiency, since traditional models such as the double exponential model are not coupled with circuit responses. The proposed artificial neural network (ANN) model shows a great prediction accuracy for single-event transient currents in 12nm FinFET technology under different time, linear energy transfer (LET), bias voltage, and strike positions. The trained model can be implemented into SPICE with Verilog-A for circuit-level simulation, and its validity in a 7-stage inverter chain and a 6T SRAM are demonstrated to provide the rapid guidance for radiation reliability. © 2023 IEEE.

关键词： FinFET machine learning neural network Single-event transient

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FEA simulation and modeling for fan-out package design 24

FEA simulation and modeling for fan-out package design

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24th Electronics Packaging Technology Conference, EPTC 2022

作者： Mandal, Rathin Institute of Microelectronics A-STAR

ISBN: (纸本)9798350398854

The fan-out package technology is introduced for package miniaturization, better electrical performance and lower cost. In this paper we are presenting wafer level warpage prediction followed by package stress and warpage, board level temperature cycling reliability and solder ball shear test modeling for a reliable package design. A modeling methodology for wafer level warpage is presented here with cure shrinkage material properties for polymeric materials. Cure shrinkage material property is showing around 35% more wafer level warpage than without cure shrinkage. Wafer warpage increased by 1.340mm for every 10 micron meter photo-dielectric polyamide (PI) thickness. The package stress modeling shows critical UBM (under bump metallization) stress is at the UBM neck at -50°C. Board level reliability (BLR) for temperature cycling (TC) solder fatigue life is more than 2000 cycles for a fully populated 10mm ×10mm, 0.4mm pitch, UBM SAC-Q solder. The SAC-Q solder reliability life is more than 1.5X of SAC387. The solder ball shear test FEA modeling also shows strong integrity of copper and mold compound materials and failure occurs at the bulk solder. © 2022 IEEE.

关键词： Curing

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modeling, simulation and control of microrobots for the microfactory.

Modeling, simulation and control of microrobots for the micr...

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作者： Zhong Yang University of Louisville

学位级别：博士

Future assembly technologies will involve higher levels of automation in order to satisfy increased microscale or nanoscale precision requirements. Traditionally, assembly using a top-down robotic approach has been well-studied and applied to the microelectronics and MEMS industries, but less so in nanotechnology. With the boom of nanotechnology since the 1990s, newly designed products with new materials, coatings, and nanoparticles are gradually entering everyone's lives, while the industry has grown into a billion-dollar volume worldwide. Traditionally, nanotechnology products are assembled using bottom-up methods, such as self-assembly, rather than top-down robotic assembly. This is due to considerations of volume handling of large quantities of components, and the high cost associated with top-down manipulation requiring precision. However, bottom-up manufacturing methods have certain limitations, such as components needing to have predefined shapes and surface coatings, and the number of assembly components being limited to very few. For example, in the case of self-assembly of nano-cubes with an origami design, post-assembly manipulation of cubes in large quantities and cost-efficiency is still challenging. In this thesis, we envision a new paradigm for nanoscale assembly, realized with the help of a wafer-scale microfactory containing large numbers of MEMS microrobots. These robots will work together to enhance the throughput of the factory, while their cost will be reduced when compared to conventional nanopositioners. To fulfill the microfactory vision, numerous challenges related to design, power, control, and nanoscale task completion by these microrobots must be overcome. In this work, we study two classes of microrobots for the microfactory: stationary microrobots and mobile microrobots. For the stationary microrobots in our microfactory application, we have designed and modeled two different types of microrobots, the AFAM (Articulated Four Axes Microro

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modeling and simulation of an insulated-gate HEMT using p-SnO2 gate for high VTH design

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microelectronics JOURNAL 2023年 139卷

作者： Yi, Bo Xu, Yi Zheng, LiTian Cheng, JunJi Huang, HaiMeng Kong, MouFu Yang, HongQiang Univ Elect Sci & Technol China Sch Integrated Circuit Sci & Engn Chengdu 610054 Peoples R China

In this paper, we proposed a novel recess-free insulated-gate High Electron Mobility Transistor (HEMT) with p-SnO2 gate realizing high threshold voltage (VTH) over 2 V. p-SnO2 is used as the gate material instead of traditional Ni/Au gate. Owing to the high work function of the p-SnO2 (both wide bandgap and large electron affinity (& chi;)), the 2DEG channel under the gate region can be deeply depleted realizing high VTH even with thick AlGaN barrier over 10 nm, which also ensures high channel mobility. An analytical model is presented and verified by experimentally calibrated TCAD simulation. Results show that for a 25 nm Al2O3, VTH of the proposed HEMT reaches 3.1 V with p-SnO2 doping NA = 5 x 1019 cm -3, which is-2.5 V higher than that of a conventional MIS-HEMT with the same parameters. Moreover, the specific on-resistance (Ron,sp) of the proposed HEMT is only 1.31 m & omega;cm2, which is reduced by 54.8% compared with that of a recessed-gate MIS-HEMT with the same VTH of-2.2 V.

关键词： Recess-free MIS-HEMT High threshold voltage p-SnO2 gate Low specific on-resistance

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Hardware Implementation of Optimized LeNet-5 2

Hardware Implementation of Optimized LeNet-5

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2nd International Conference on Computational modeling, simulation and Data Analysis, CMSDA 2022

作者： Ju, Junlei Liu, Cheng School of Microelectronics Shanghai University Shanghai China

ISBN: (纸本)9798350345759

Convolutional Neural Network (CNN), a feedforward neural network, is widely used in large-scale machine learning tasks such as image recognition, image classification, and object detection. Although CNN has strong performance, its application in daily embedded systems is limited due to the complex network hierarchy and a large amount of data. In this paper, the LeNet-5 network structure is optimized. The recognition accuracy of the optimized network on the MNIST dataset is 98.32%, but the number of weights is reduced by more than ten times compared with the LeNet-5 network, and data quantization is used to convert the weights into 8-bit fixed-point numbers, which is more suitable for deployment in the hardware with limited resources and power consumption. At the same time, different hardware structures and optimization strategies are designed for each layer of the network, and the convolution, pooling and fully connected layers are computed in parallel and optimized using methods such as loop unrolling and pipelining. Finally, the feasibility of the hardware design is verified by simulating each layer using the MNIST dataset and quantized weights. © 2022 IEEE.

关键词： Image recognition

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modeling Advanced Spintronic Based Magnetoresistive Memory

Modeling Advanced Spintronic Based Magnetoresistive Memory

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2022 International Conference on Microwave and THzTechnologies, Wireless Communications and OptoElectronics, IRPhE 2022

作者： Fiorentini, Simone Bendra, Mario Ender, Johannes Hadámek, Tomáš Loch, Wilton Jaciel Jørstad, Nils Petter Orio, Roberto Goes, Wolfgang Selberherr, Siegfried Sverdlov, Viktor Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics TU Wien Austria Institute for Microelectronics TU Wien Austria Silvaco Europe Ltd. Cambridge United Kingdom

ISBN: (纸本)9781839537868

Spintronic based magnetoresistive memory shows an increasing potential in replacing conventional charge based memory for stand-alone and embedded applications. Accurate simulation tools, providing a comprehensive evaluation of the spin torques and magnetization dynamics in structures with several ferromagnetic and nonmagnetic metal layers separated by tunnel barriers, are required to design advanced magnetoresitive memory cells. We demonstrate that the coupled spin and charge drift-diffusion transport approach, extended to describe magnetic tunnel junctions and augmented with temperature, is suitable to describe complex magnetoresitive memory cells with two reference layers controlled by spin torques. © IET Conference Proceedings 2022.

关键词： Tunnel junctions

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Study on the influence of hardmask morphology on substrate profile in plasma etching process 14

Study on the influence of hardmask morphology on substrate p...

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Advanced Etch Technology and Process Integration for Nanopatterning XIV

作者： Lei, Yuzhang Hu, Ziyi Zhai, Yuxuan Shao, Hua Li, Junjie Chen, Rui Yan, Jiang School of Information Science and Technology North China University of Technology Beijing100144 China State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9781510686441

In plasma etching process, hardmask is an important protective material for substrates, especially for deep silicon etching. The consumption and deformation of hardmask affect the substrate etching profiles, which can severely impact the devices performance. The scaling of devices and more complex structures demand for higher performance of hardmask. However it is difficult and costly to characterize the evolution of hardmask profile during etching. modeling is an effective manner to overcome this challenge. In this paper, we take the Si etching by SF6/O2 mix gas as the modeling target and conduct theoretic study, using the commercial simulation software named PEGASUS. We explored the effects of different hardmask parameters including thickness, open CD and sidewall angle on substrate etching profile, and characterize the etching rate, sidewall angles, and profile defects such as bowing. This study seeks to provide insight into the correlation, between hardmask morphology and etching profile, and provides theoretical support for the stack structure design and process optimization. © 2025 SPIE.

关键词： Plasma etching

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Nanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device

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ACS APPLIED MATERIALS & INTERFACES 2023年第2期15卷 3119-3130页

作者： Corley-Wiciak, Cedric Richter, Carsten Zoellner, Marvin H. Zaitsev, Ignatii Manganelli, Costanza L. Zatterin, Edoardo Schulli, Tobias U. Corley-Wiciak, Agnieszka A. Katzer, Jens Reichmann, Felix Klesse, Wolfgang M. Hendrickx, Nico W. Sammak, Amir Veldhorst, Menno Scappucci, Giordano Virgilio, Michele Capellini, Giovanni Leibniz Inst Kristallzuchtung IKZ Berlin Germany Leibniz Inst Innovat Mikroelekt IHP D-15236 Frankfurt Oder Germany European Synchrotron Radiat Facil ESRF F-38043 Grenoble France Delft Univ Technol QuTech & Kavli Inst Nanosci NL-2628 CJ Delft Netherlands QuTech & Netherlands Org Appl Sci Res TNO NL-2628 CK Delft Netherlands Univ Pisa Dept Phys Enrico Fermi I-56126 Pisa Italy Univ Roma Tre Dipartimento Sci I-00146 Rome Italy

A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters. This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approximately 50 nm. Two different spatial scales governing the strain field fluctuations in proximity of the qubits are observed at <100 nm and >1 mu m, respectively. The short-ranged fluctuations have a typical bandwidth of 2 x 10-4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations, it is estimated that this strain fluctuation is increased up to 6 x 10-4 at cryogenic temperature. The longer ranged fluctuations are of the 10-3 order and are associated with misfit dislocations in the plastically relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 mu eV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material-related inhomogeneities may feed into further modeling for optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.

关键词： lattice strain synchrotron X-ray diffraction quantum computing silicon germanium thermomechanical FEM simulation

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TCAD simulations of Radiation Damage in 4H-SiC

TCAD Simulations of Radiation Damage in 4H-SiC

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Austrian Workshop on microelectronics (Austrochip)

作者： Jürgen Burin Christopher Hahn Philipp Gaggl Andreas Gsponer Simon Waid Thomas Bergauer Institute of High Energy Physics Austrian Academy of Sciences Vienna Austria

ISBN: (数字)9798331516178

ISBN: (纸本)9798331516185

In this paper we present simulation based radiation damage modeling of 4H silicon carbide (SiC) using the technology computer aided design (TCAD) tools for up to 1 kV forward and backward bias. After verifying the TCAD framework from Global TCAD Solutions (G TS) against Sentaurus simulations for silicon we use it to approximate measurements of neutron-irradiated 4H-SiC particle detectors, i.e., p-i-n diodes. Based on our simulations we are not only able to evaluate the accuracy of the predictions but also to provide an explanation for the almost negligible current of radiated devices under high forward bias.

关键词： design automation Silicon carbide Current measurement Radiation detectors Particle measurements Silicon microelectronics P-i-n diodes Electric fields Current

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Improvement of simulation-based analog circuit sizing using design-space transformation 16

Improvement of simulation-based analog circuit sizing using ...

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2021 International Conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th Conference on PhD Research in microelectronics and Electronics, PRIME 2021

作者： Schweikardt, Matthias Scheible, Jürgen Electronics and Drives Reutlingen University Reutlingen Germany

ISBN: (纸本)9783800755899

This paper presents an improvement in usability and integrity of simulation-based analog circuit sizing. Instead of using geometrical sizing parameters (width, length), a transformed design-space, consisting exclusively of electrical parameters (branch currents, efficiencies and speed) is utilized. This design-space is explored more efficiently by optimizers. Moreover, this design-space can be reduced without affecting the quality of the result. The method is illustrated on two application examples, a symmetrical and a miller operational amplifier. Sizing the circuits using the transformed design-space showed significant reduction in required circuit simulations (up to 11x faster), better convergence, without loss in quality. © VDE VERLAG GMBH.

关键词： Circuit simulation

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