The effects of varying layout geometries and various thermal boundary resistances(TBRs)on the thermal resistance of multi-finger AlGaN/GaN HEMTs are thoroughly investigated using a combination of a two-dimensional ele...
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The effects of varying layout geometries and various thermal boundary resistances(TBRs)on the thermal resistance of multi-finger AlGaN/GaN HEMTs are thoroughly investigated using a combination of a two-dimensional electro-thermal model coupled with the three-dimensional thermal *** measurement using micro-Raman thermography is performed to verify and enhance the accuracy of the thermal *** results indicate that thermal resistance weakly depends on the layout design because of the high thermal conductivity of ***,the analysis reveals that optimizing the TBR of the device could efficiently reduce the thermal resistance since TBR takes a significant proportion of the total thermal resistance.
In this paper, dielectric charging process in dielectrics under bias voltage is investigated. Dielectric materials, used in numerous devices in microelectronics, can be subjected to significant electrical stress. Thes...
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In this paper, dielectric charging process in dielectrics under bias voltage is investigated. Dielectric materials, used in numerous devices in microelectronics, can be subjected to significant electrical stress. These high electric fields impact the device lifetime. Actuation voltage measurements of capacitive RF MEMS as a function of stress time have been performed. Results show that the actuation voltage varies because of charge storage in the dielectric thin film. In this work a simulation code has been developed to model charge transport phenomena in insulators. This model takes into account tunnel and thermal effects in the dielectric and at the dielectric-metal interfaces. Thanks to this model, charge carrier distribution in the dielectric layer can be calculated. The actuation bias shift versus time, which can be responsible for RF capacitive structure failure, can also be determined. Experimental results can be reproduced thanks to simulations. This simulation tool is then used to define the optimal operating voltage value for a given RF MEMS device. It may also be used to assist in device design in microelectronics. Indeed for a given material set, the optimal operating voltage value is calculated as a function of device properties.
Electronic design Automation (EDA) is essential for the design of large-scale microelectronic systems. In this article, EDA methodologies, techniques, and algorithms used to develop superconductive computing systems a...
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Electronic design Automation (EDA) is essential for the design of large-scale microelectronic systems. In this article, EDA methodologies, techniques, and algorithms used to develop superconductive computing systems are reviewed. The semicustom standard cell-based design flow, common in conventional CMOS circuits, is widely adopted in modern superconductive digital circuits. Differences and issues in CAD flows as compared to CMOS design methodologies are highlighted. The most common stages of these design flows, from high-level simulation to physical layout, are described. These stages are grouped into three areas: simulation/modeling, synthesis/place and route, and verification. Modern approaches and tools for superconductive circuits are reviewed for each of these areas.
High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their opera...
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High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their operation. This leads to the need for electro-thermal 2/3-D numerical modeling and simulation in power electronics as an efficient tool for analysis and optimization of device structure design and identification of critical regions. In this paper we present an analysis and geometry optimization of a high power pin diode structure supported by advanced 2-D mixed mode electro-thermal device and circuit simulation. Lowering of the operation temperature by better power management and heat dissipation due to an optimized structure design will allow withstanding higher current pulses and suppressing the damage of the analyzed structure by thermal breakdown. (C) 2011 Elsevier Ltd. All rights reserved.
This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model base...
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This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 M Omega junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load. (c) 2005 Elsevier Ltd. All rights reserved.
New transparent memory test algorithms for semiconductor memory are presented in the paper along with the modified memory testing simulation package MAP. The test algorithms allow detecting memory read errors - the er...
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ISBN:
(纸本)0819439002
New transparent memory test algorithms for semiconductor memory are presented in the paper along with the modified memory testing simulation package MAP. The test algorithms allow detecting memory read errors - the error type that was not covered in the previous research.
This paper explores the recent history and diversity of this remarkable technology, with emphasis on recent advances in the more traditional device types (traveling-wave tube and klystron), as well as more recent inno...
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This paper explores the recent history and diversity of this remarkable technology, with emphasis on recent advances in the more traditional device types (traveling-wave tube and klystron), as well as more recent innovations such as the in microwave power module, inductive output amplifier, fast-wave devices, ultrahigh-power sources, and RF vacuum microelectronics. These advances can be credited to a combination of device innovation, enhanced understanding gained through improved modeling and design, the Introduction of superior materials and sub-assembly components and the development of advanced vacuum processing and manufacturing techniques.
The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism, Instead, wide bit-fields containing net-values for several different ...
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The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism, Instead, wide bit-fields containing net-values for several different times are used to resolve out-of-order events, Bit-parallel operations are performed to simulate;gates at the required times, The MDP technique was originally designed to be implemented in hardware, but the current software version of the algorithm has proven to be competitive with conventional event-driven multidelay simulation, Two versions of the MDP technique are presented in this paper, fixed alignment and variable alignment, The fixed alignment algorithm provides bit-fields that are wide enough to capture any event that could occur during the simulation of an input vector, while the variable alignment algorithm uses a minimum-width bit field which is just wide enough to capture those events that could occur at an individual step in the simulation, A prototype hardware design is discussed briefly.
The realization of virtual prototyping of electronic packages depends on the capability and reliability of multiphysics modeling. This paper focuses on the methods and solutions of combined thermal and thermo-mechanic...
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The realization of virtual prototyping of electronic packages depends on the capability and reliability of multiphysics modeling. This paper focuses on the methods and solutions of combined thermal and thermo-mechanical modeling. The package-level thermal behaviors for various kinds of packages are discussed first through the thermal simulation. The impact of internal package design on thermal performance is highlighted. Then the methods and solutions of combined thermal and thermo-mechanical modeling are addressed in detail. The strong interactions of thermal and mechanical simulations, as well as the trade-off between thermal and mechanical designs are discussed through two case studies. The benefit of moisture behavior modeling for the package design is also briefed in this paper. (C) 2004 Elsevier Ltd. All rights reserved.
This paper presents thermal simulations for reliability-oriented design of planar transformers for medium-power, high-frequency DC-DC converters. The modeling approach is based on accurate 3D finite-element thermal si...
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This paper presents thermal simulations for reliability-oriented design of planar transformers for medium-power, high-frequency DC-DC converters. The modeling approach is based on accurate 3D finite-element thermal simulation of the transformer structure;inputs to the finite-element thermal model are the magnetic and electrical power losses extracted by experimental characterization of a planar transformer test-bench we designed and assembled. The simulation results are compared with those of infra-red thermal measurements. The simulations allowed to evaluate the effect of frequency and output current on the temperature distribution inside the transformer, thus setting limits for reliable operation, and to analyze alternative designs aimed at improving thermal management and, consequently the transformer reliability. (C) 2010 Elsevier Ltd. All rights reserved.
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