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54 篇 会议

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检索条件"任意字段=Designers Forum - Design, Automation and Test in Europe Conference and Exhibition, DATE 04"

共 54 条记录，以下是1-10 订阅

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designers's forum-design, automation and test in europe conference and exhibition, date 04

Designers's forum-design, automation and test in Europe conf...

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designers forum - design, automation and test in europe conference and exhibition, date 04

ISBN: (纸本)0769520855

The proceedings contains 59 papers from the conference on designers' forum - design, automation and test in europe conference and exhibition, date 04. The topics discussed include: highly digital, low-cost design of statistic signal acquisition in SoCs;low power analyogue 90 degree phase shifter;an inductance modeling flow seamlessly integrated in the RF IC design chain;design of very deep pipelined multipliers for FPGAs;channel decoder architecture for 3G mobile wireless terminals;a scalable implementation of a reconfigurable WCDMA rake reciever and modeling and analysis of heterogenous industrial networks architectures.

关键词： Integrated circuits

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designers' forum - design, automation and test in europe conference and exhibition, date 2004

Designers' Forum - Design, Automation and Test in Europe Con...

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design, automation and test in europe conference and exhibition, date 2004

ISBN: (纸本)0769520855

The proceedings contain 323 papers. The topics discussed include: value-conscious cache: simple technique for reducing cache access power;arithmetic reasoning in DPLL-based SAT solving;using BDDs and ZBDDs for efficient identification of testable path delay faults;Z-sets and Z-detections: circuit characteristics that simplify fault diagnosis;loop shifting and compaction for the high-level synthesis of designs with complex control flow;re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus;a mapping strategy for resource-efficient network processing on multiprocessor SoCs;design of sub-10-picoseconds on-chip time measurement circuit;automated, accurate macromodelling of digital aggressors for power/ground/substrate noise prediction;a high-speed transceiver architecture implementable as synthesizable IP core;and verification of a microcontroller IP core for system-on-a-chip designs using low-cost prototyping environments.

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designers' forum design, automation and test in europe conference and exhibition

Designers' Forum Design, Automation and Test in Europe Confe...

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design, automation and test in europe conference and exhibition

Presents the front cover of the proceedings.

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designers' forum design, automation and test in europe conference and exhibition

Designers' Forum Design, Automation and Test in Europe Confe...

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design, automation and test in europe conference and exhibition

Presents the title -page of the proceedings record.

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date 2025 PhD forum

DATE 2025 PhD Forum

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design, automation and test in europe conference and exhibition

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PFASware: Quantifying the Environmental Impact of Per- and Polyfluoroalkyl Substances (PFAS) in Computing Systems

PFASware: Quantifying the Environmental Impact of Per- and P...

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design, automation and test in europe conference and exhibition

作者： Mariam Elgamal Abdulrahman Mahmoud Gu-Yeon Wei David Brooks Gage Hills Harvard School of Engineering and Applied Sciences (SEAS) Mohamed Bin Zayed University of AI (MBZUAI)

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

PFAS (per-and poly-fluoroalkyl substances), also known as forever chemicals, are widely used in electronics and semiconductor manufacturing. PFAS are environmentally persistent and bioaccumulative synthetic chemicals, which have recently received considerable regulatory attention. Manufacturing semiconductors and electronics, including integrated circuits (IC), batteries, displays, etc., currently accounts for a staggering 10% of the total PFAS-containing fluoropolymers used in europe alone. Now, computer system designers have an opportunity to reduce the use of PFAS in semiconductors and electronics at the design phase. In this work, we quantify the environmental impact of PFAS in computing systems, and outline how designers can optimize their designs to use less PFAS. We show that manufacturing an IC design at a 7 nm technology node using Extreme Ultraviolet (EUV) lithography uses 20% less volume of PFAS-containing chemicals versus manufacturing the same design at a 7 nm node using Deep Ultraviolet (DUV) immersion lithography (instead of EUV). We also show that manufacturing an IC design at a 16 nm technology node results in 15% less volume of PFAS than manufacturing the same design at a 28 nm node due to its smaller area.

关键词： Integrated circuits Extreme ultraviolet lithography Ultraviolet sources europe Semiconductor device manufacture Batteries Chemicals

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Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis

Clock and Power Supply-Aware High Accuracy Phase Interpolato...

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design, automation and test in europe conference and exhibition

作者： Siou-Sian Lin Shih-Yu Chen Yu-Ping Huang Tzu-Chuan Lin Hung-Ming Chen Wei-Zen Chen Inst. of Electronics National Yang Ming Chiao Tung University Hsinchu City Taiwan

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Due to popular requests from the designers of clock and data recovery (CDR) regarding the inefficiency of generating high accuracy phase interpolator (PI), in this work, we have developed a layout generator for such circuit, different from conventional constraint-driven works. In the first stage, we propose a customized template floorplanning plus pin generation demanded by the users. In the second stage, in order to generate high accuracy layout, we implement a gridless router for signal, power supply and clock. Experiments with several configurations indicate that our approach can generate high-quality corresponding layouts that align with user expectations, and even surpass the quality of manual designs on structurally regular high-performance PIs, which are not easy and efficient to be generated by prior primitive/grid-based methods.

关键词： Accuracy Power supplies Layout europe Manuals Analog circuits Routing Generators Pins Clocks

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Efficient SAT-Based Bounded Model Checking of Evolving Systems

Efficient SAT-Based Bounded Model Checking of Evolving Syste...

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design, automation and test in europe conference and exhibition

作者： Sophie Andrews Matthew Sotoudeh Clark Barrett Stanford University

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

SAT-based verification is a common technique used by industry practitioners to find bugs in computer systems. However, these systems are rarely designed in a single step: instead, designers repeatedly make small modifications, reverifying after each change. With current tools, this reverification step takes as long as a full, from-scratch verification, even if the design has only been modified slightly. We propose a novel SAT-based verification technique that performs significantly better than the naïve approach in the setting of evolving systems. The key idea is to reuse information learned during the verification of earlier versions of the system to speed up the verification of later versions. We instantiate our technique in a bounded model checking tool for SystemVerilog code and apply it to a new benchmark set based on real edit history for a set of open source RISC-V cores. This new benchmark set is now publicly available for further research on verification of evolving systems. Our tool, PrediCore, significantly improves the time required to verify properties on later versions of the cores compared to the current state-of-the-art, verify-from-scratch approach.

关键词： Industries Software algorithms Computer bugs europe Model checking Benchmark testing Prediction algorithms Hardware Software History

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INTO-OA: Interpretable Topology Optimization for Operational Amplifiers

INTO-OA: Interpretable Topology Optimization for Operational...

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design, automation and test in europe conference and exhibition

作者： Jinyi Shen Fan Yang Li Shang Zhaori Bi Changhao Yan Dian Zhou Xuan Zeng State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China State Key Laboratory of Integrated Chips and Systems School of Computer Science Fudan University Shanghai China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper presents INTO-OA, an interpretable topology optimization method for operational amplifiers (op-amps). We propose a Bayesian optimization-based approach to effectively explore the high-dimensional, discrete topology design space of op-amps. Our method integrates a Gaussian process surrogate model with the Weisfeiler-Lehman graph kernel to extract structural features from a dedicated circuit graph representation. It also employs a candidate generation strategy that combines random sampling with mutation to balance global exploration and local exploitation. Additionally, INTO-OA enhances interpretability by assessing the impact of circuit structures on performance, providing designers with valuable insights into generated topologies and enabling the interpretable refinement of existing designs. Experimental results demonstrate that INTO-OA achieves higher success rates, a 1.84× to 19.10x improvement in op-amp performance, and a 3.20x to 14.33× increase in topology optimization efficiency compared to state-of-the-art methods.

关键词： Operational amplifiers Optimization methods europe Gaussian processes Feature extraction Topology Space exploration Bayes methods Kernel Integrated circuit modeling

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Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework

Compatibility Graph Assisted Automatic Hardware Trojan Inser...

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design, automation and test in europe conference and exhibition

作者： Gaurav Kumar Ashfaq Hussain Shaik Anjum Riaz Yamuna Prasad Satyadev Ahlawat Dept. of EE Indian Institute of Technology Jammu India Dept. of CSE Indian Institute of Technology Jammu India

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Hardware Trojans (HTs) pose substantial security threats to Integrated Circuits (ICs), compromising their integrity, confidentiality, and functionality. Various HT detection methods have been developed to mitigate these risks. However, the limited availability of comprehensive HT benchmarks necessitates designers to create their own for evaluation purposes. Moreover, the existing benchmarks exhibit several deficiencies, including a restricted range of trigger nodes, susceptibility to detection through random patterns, lengthy HT instance creation and validation process, and a limited number of HT instances per circuit. To address these limitations, we propose a Compatibility Graph assisted automatic Hardware Trojan insertion framework for HT benchmark generation. Given a netlist, this framework generates a design incorporating single or multiple HT instances according to user-defined properties. It allows various configurations of HTs, such as a large number of trigger nodes, low activation probability and large number of unique HT instances. The experimental results demonstrate that the generated HT benchmarks exhibit exceptional resistance to state-of-the-art HT detection schemes. Additionally, the proposed framework achieves an average improvement of 37815.7x and 989.4x over the insertion times of the Random and Reinforcement Learning based HT insertion frameworks, respectively.

关键词： Integrated circuits Resistance Hardware security europe Reinforcement learning Benchmark testing Trojan horses Digital circuits

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