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54 篇 会议

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检索条件"任意字段=Designers Forum - Design, Automation and Test in Europe Conference and Exhibition, DATE 04"

共 54 条记录，以下是41-50 订阅

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2009 EDAA PhD forum at date

2009 EDAA PhD forum at DATE

引用

design, automation and test in europe conference and exhibition

关键词： Algorithm design and analysis Performance analysis Optical design design optimization System-on-a-chip Network-on-a-chip Laboratories Image analysis Pattern analysis Space exploration

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2011 EDAA/ACM SIGDA PhD forum at date in Grenoble

2011 EDAA/ACM SIGDA PhD Forum at DATE in Grenoble

引用

design, automation and test in europe conference and exhibition

The EDAA/ACM PhD forum is part of the date conference and hosted by ACM SIGDA and the european design automation Association (EDAA). It offers the opportunity for PhD students to present their thesis work to a broad audience in the design, automation and test community from academia and industry. During the presentation at the date conference, it helps students to establish contacts. Also, representatives from industry and academia get a glance of state-of-the-art research in design, automation and test. The review process resulted in the selection of the PhD students listed below. We thank the EDAA, ACM SIGDA and date for making this forum possible. Peter Marwedel (Chair, 2011 EDAA I A CM PhD forum at date).

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EDAA/date PhD forum

EDAA/DATE PhD Forum

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design, automation and test in europe conference and exhibition

The EDAA/date PhD forum offers the opportunity for PhD students to present their thesis work to a broad audience in the design automation and test community from both academia and industry. During the presentation at the date conference it helps students to establish contacts when entering the job market. On the other side, representatives from industry and academia get a glance of state-ofthe-art research in design automation and test. This year we received a total of 60 submissions out of which 46 have been accepted for presentation at a dinner reception. The review process was conducted by a team of 10 internationally renowned reviewers. Our thanks go to all presenters, the PhD forum Committee and all who were involved in conducting the review process and arranging and organizing the forum event at date. We also thank the EDAA and date organizers and representatives for making this forum possible.

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Cross-layer resilience challenges: Metrics and optimization 10

Cross-layer resilience challenges: Metrics and optimization

引用

design, automation and test in europe conference and exhibition

作者： Subhasish Mitra Kevin Brelsford Pia N. Sanda Robust Systems Group Department of EE and Department of CS University of Stanford Stanford CA USA IBM Corporation Poughkeepsie NY USA

ISBN: (纸本)9783981080162

With increasing sources of disturbances in the underlying hardware, a key challenge in design of robust systems is to meet user expectations at required cost. Cross-layer resilience techniques, implemented across multiple layers of the system stack and designed to work together, can help system designers build effective robust systems at the desired cost point. This paper brings to the forefront two major cross-layer resilience challenges: 1. Quantification and validation of the effectiveness of a cross-layer resilience approach to robust system design in overcoming hardware reliability challenges. 2. Global optimization of a robust system design using cross-layer resilience techniques.

关键词： Resilience Robustness Hardware Circuits Error correction design optimization Built-in self-test System-on-a-chip Cost function Logic

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designers' forum Committee 05

Designers' Forum Committee

引用

Proceedings of the conference on design, automation and test in europe - Volume 3

No abstract available.

ISBN: (纸本)9780769522883

No abstract available.

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Analysis and minimization of test time in a combined BIST and external test approach

Analysis and minimization of test time in a combined BIST an...

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design, automation and test in europe conference and exhibition

作者： M. Sugihara H. date H. Yasuura Department of Computer Science and Communication Engineering Kyushu University Fukuoka Japan Institute of Systems & Fukuoka SRP Center Building Information Technologies KYUSHU Fukuoka Japan

In this paper, an, analysis of test time by CBET (which is an acronym for Combination of BIST and External test) test approach is presented. The analysis validates that CBET test approach can achieve shorter testing time than both external test and BIST in many situations. An efficient test time minimization algorithm for CBET-based LSIs is also proposed. It uses several characteristics of CBET test approach derived by the analysis to reduce computation time to find the optimum test sets. The algorithm helps designers to save their precious design time.

关键词： Built-in self-test Circuit testing System testing Minimization methods Algorithm design and analysis System-on-a-chip Processor scheduling Computer science Information technology Cities and towns

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Automated feature localization for dynamically generated SystemC designs 15

Automated feature localization for dynamically generated Sys...

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design, automation and test in europe conference and exhibition

作者： Jannis Stoppe Robert Wille Rolf Drechsler Cyber-Physical Systems DFKI GmbH Bremen Germany Group of Computer Architecture University of Bremen Bremen Germany

ISBN: (纸本)9783981537048

Due to the large complexity of today's circuits and systems, all components e.g. in a System on Chip (SoC) cannot be designed from scratch anymore. As a consequence, designers frequently work on components which they did not create themselves and, hence, design understanding becomes a crucial issue. Approaches for feature localization help by pinpointing to distinguished characteristics of a design. However, existing approaches for feature localization mainly focused on the Register Transfer Level; existing solutions for the Electronic System Level (using languages such as SystemC) have severe limits. In this work, we propose an approach for advanced feature localization in SystemC designs. By this, we overcome major limitations of previously proposed solutions, in particular the missing support for dynamically generated designs, while keeping the proposed solution as non-intrusive as possible. The benefits of our approach are confirmed by means of a case study.

关键词： Receivers Switches Programming automation europe Weaving System-on-chip

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Formal Methods for Ranking Counterexamples Through Assumption Mining 12

Formal Methods for Ranking Counterexamples Through Assumptio...

引用

design, automation & test in europe conference & exhibition

作者： Srobona Mitra Ansuman Banerjee Pallab Dasgupta Indian Institute of Technology Kharagpur Kharagpur India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9783981080186

Bug-fixing in deeply embedded portions of the logic is typically accompanied by the post-facto addition to new assertions which cover the bug scenario. Formally verifying properties defined over such deeply embedded portions of the logic is challenging because formal methods do not scale to the size of the entire logic, and verifying the property on the embedded logic in isolation typically throws up a large number of counterexamples, many of which are spurious because the scenarios they depict are not possible in the entire logic. In this paper we introduce the notion of ranking the counterexamples so that only the most likely counterexamples are presented to the designer. Our ranking is based on assume properties mined from simulation traces of the entire logic. We define a metric to compute a belief for each assume property that is mined, and rank counterexamples based on their conflicts with the mined assume properties. Experimental results demonstrate an amazing correlation between the real counterexamples (if they exist) and the proposed ranking metric, thereby establishing the proposed method as a very promising verification approach.

关键词： Formal logic designers Conflict (Psychology) embedding Beliefs Entire mining Metric Metronidazole

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Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique 15

Leakage power reduction for deeply-scaled FinFET circuits op...

引用

design, automation and test in europe conference and exhibition

作者： Ji Li Qing Xie Yanzhi Wang Shahin Nazarian Massoud Pedram Department of Electrical Engineering University of Southern California Los Angeles CA USA

ISBN: (纸本)9783981537048

With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in the near- and super-threshold operation regimes. The impacts of Gate-Length Biasing (GLB) on circuit speed and leakage power are first studied using one of the most advanced technology nodes - a 7nm FinFET technology. Then multiple standard cell libraries using different leakage reduction techniques, such as GLB and Dual-V T , are built in multiple operating regimes at this technology node. It is demonstrated that, compared to Dual-V T , GLB is a more suitable technique for the advanced 7nm FinFET technology due to its capability of delivering a finer-grained trade-off between the leakage power and circuit speed, not to mention the lower manufacturing cost. The circuit synthesis results of a variety of ISCAS benchmark circuits using the presented GLB 7nm FinFET cell libraries show up to 70% leakage improvement with zero degradation in circuit speed in the near- and super-threshold regimes, respectively, compared to the standard 7nm FinFET cell library.

关键词： Decision support systems automation europe FinFETs Standards Libraries Benchmark testing

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A flexible specification framework for hardware-software codesign 00

A flexible specification framework for hardware-software cod...

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design, automation and test in europe conference and exhibition

作者： Jose Manuel Moya Santiago Dominguez Francisco Moya Juan Carlos Lopez Universidad de Castilla-La Mancha Departamento de Informática ESI. P° Universidad 4 13071 Ciudad Read Spain

ISBN: (纸本)0769505376

In this poster, we present a new specification technique for complex hardware-software systems, based on standard high-level programming languages, such as C, C++, Java, Scheme, or Ada, without extensions or semantic changes. Unlike previous approaches, the designer may choose the model of computation and the specification language that best suits her needs, while still being able to formally verify the correctness of the specification. The details of the available hardware and software resources, and the implementation of the different models of computation are encapsulated in libraries to maximize reuse in system specifications.

关键词： Hardware/software co-design MODEL CALCULATION Specifications system specifications ADA (PROGRAMMING LANGUAGE) specification description language Posters designers high-level programming languages accuracy class Libraries reuse

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