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modeling and testing of a digital distance relay MATLAB/SIMULINK

Modeling and testing of a digital distance relay MATLAB/SIMU...

引用

Annual North-American Power symposium

作者： Li-Cheng Wu Chih-Wen Liu Ching-Shan Chen Department of Electrical Engineering National Taiwan University Taipei Taiwan

This paper describes modelling and testing of a digital distance relay for transmission line protection using MATLAB/SIMULINK. SIMULINK's power system blockset (PSB) is used for detailed modelling of a power system network and fault simulation. MATLAB is used to implement programs of digital distance relaying algorithms and to serve as main software environment. The technique is an interactive simulation environment for relaying algorithm design and evaluation. The basic principles of a digital distance relay and some related filtering techniques are also described in this paper. A 345 kV, 100 km transmission line and a MHO type distance relay are selected as examples for fault simulation and relay testing. Some simulation results are given.

关键词： Mathematical model Testing Protective relaying MATLAB Power system modeling Power system simulation Power system relaying Power system protection digital relays Power system faults

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A high-level tool for the design of custom image processing systems

A high-level tool for the design of custom image processing ...

引用

Euromicro symposium on digital System design

作者： S. Martins J.C. Alves FEUP-DEEC Porto Portugal INESC Porto FEUP-DEEC Porto Portugal

Real-time image processing is a computational intensive task with applications in various engineering fields. In several image processing applications, a significant amount of computing power is committed to image enhancement operations, basic segmentation and identification of regions of interest for further analysis. Such type of front-end processing can be done efficiently by custom data-flow processors closely coupled to an image sensor. This paper proposes a visual design environment to support the high-level design of custom data-flow processors for real-time image analysis applications. The tool is embedded in Matlab/Simulink, and the system modeling is done using a library of blocks that implement common low-level image processing operations. Functional validation is performed efficiently by the simulation engine of Simulink in a frame by frame basis, using the functions provided by the image processing toolbox in Matlab. The automatic generation of a synthesizable RTL model guarantees a logic implementation of the system that complies to the high-level model validated, under constraints imposed by the user and the target reconfigurable device.

关键词： Image processing Power engineering computing Image analysis Mathematical model Power engineering and energy Image enhancement Image segmentation Image sensors modeling Libraries

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F.A.S.T. FIR filter synthesis

F.A.S.T. FIR filter synthesis

引用

Southeastern symposium on System Theory

作者： R.W. Mehler Dian Zhou University of Texas Dallas Dallas TX USA

We present an architectural synthesizer that produces highly optimized designs from system level specifications while requiring little operator effort or knowledge of digital design techniques. With the initial application of the synthesizer limited to digital finite impulse response (FlR) filters, the synthesizer automatically optimizes both the architecture and filter coefficients, giving results competitive with the best efforts of human designers and other high level tools. We also present a near-optimal and eminently practical algorithm for subexpression sharing in hardware multipliers.

关键词： Finite impulse response filter Synthesizers Hardware design languages design optimization digital filters Signal processing algorithms design engineering Algorithm design and analysis Matched filters design automation

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Embedded object architecture

Embedded object architecture

引用

Euromicro symposium on digital System design

作者： T. Vallius J. Roning Computer Engineering Laboratory University of Oulu Oulu Finland

Traditionally, the embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems impossible for many companies, and in research facilities it hinders the testing of new research results with real embedded systems. We previously presented an easy and fast embedded system development concept based on embedded objects. The embedded object concept (EOC) utilizes common object oriented methods used in software by applying them to combined Lego-like software-hardware entities. This concept enables people without comprehensive knowledge in electronics design to create new embedded systems. In this paper we present a physical and logical architecture for this concept.

关键词： Embedded system Hardware Poles and towers Embedded software Object oriented modeling Computer architecture System testing Embedded computing design engineering Object oriented methods

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modeling of substrate noise block properties for early prediction

Modeling of substrate noise block properties for early predi...

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IEEE International symposium on Circuits and Systems (ISCAS)

作者： G. Blakiewicz M. Chrzanowska-Jeske Department of Microelectronic Systems Gdansk University of Technology Gdansk Poland Electrical & Computer Engineering Portland State University Portland USA

We propose a new approach to substrate noise modeling in early design planning of mixed-signal systems-on-chips (MS-SOCs). It can be applied to a system without any detailed knowledge (physical-layout) about its building blocks. We assume and justify that, in early prediction, only the most significant noise sources of substrate noise need to be considered. To capture important properties of substrate noise we consider the frequency-dependent sensitivity of analog blocks and a noise injection model for noisy digital blocks. We use experimental substrate noise simulations to build our models, and give suggestions on how to estimate noise parameters for building blocks of MS-SOC.

关键词： Predictive models Substrates Semiconductor device noise Circuit noise Integrated circuit noise Frequency Integrated circuit reliability Microelectronics design engineering Technology planning

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A suite of visual languages for statistical survey specification

A suite of visual languages for statistical survey specifica...

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IEEE symposium on Visual Languages and human Centric Computing (VL/HCC)

作者： Chul Hwee Kim J. Hosking J. Grundy Department of Computer Science University of Auckland Auckland New Zealand Department of Electrical and Computer Engineering University of Auckland Auckland New Zealand

We describe SDL, an integrated suite of visual languages aimed at supporting the process of designing statistical surveys. SDL comprises four diagrammatic notations: survey diagrams, survey data diagrams, survey analysis diagrams and survey process diagrams. A proof of concept environment supporting SDL is also presented, together with a cognitive dimensions evaluation of that environment and a cognitive walkthrough evaluation with a target end user - a professional statistician. These demonstrate the utility of SDL and lead us to propose development of a more comprehensive environment supporting the entire statistical survey process.

关键词： Data analysis Process design Unified modeling language design engineering Books Sampling methods Synthetic aperture sonar Software design Information analysis Performance analysis

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An 800 Mbps system interconnect modeling and simulation for high speed computing

An 800 Mbps system interconnect modeling and simulation for ...

引用

IEEE International symposium on Circuits and Systems (ISCAS)

作者： M.S. Sharawi D.N. Aloi Electrical and System Engineering Oakland University Rochester MI USA

System interconnect modeling for high speed systems is a vital bottleneck for high speed data transfer. We demonstrate the modeling process on a high speed computer differential net running at 400 MHz (800 Mbit/s) with IBM I/O cells. The modeling of the traces on the boards was done using a field solver. The transmission line matrices were used in a SPICE model, and 3-simulation scenarios were tested for this model. The obtained EYE opening of the modeled interconnect simulation was 705 mV while the measured EYE opening for the same net topology in the laboratory was 710 mV. This shows a close match between the actual behavior and the model generated. Careful modeling can be very beneficial to get a design running at first time operation.

关键词： Computational modeling Integrated circuit interconnections Personal digital assistants Frequency Connectors Electromagnetic modeling Power cables Driver circuits Wire Etching

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A new method for design of robust digital circuits

A new method for design of robust digital circuits

引用

IEEE International symposium on Quality Electronic design

作者： D. Patil S. Yun S.-J. Kim A. Cheung M. Horowitz S. Boyd Department of Electrical Engineering University of Stanford Stanford CA USA

As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat "wall" of equally critical paths, resulting in variation-sensitive designs. This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield. The method is based on adding margins on each gate delay to account for variations and using a new "soft maximum" function to combine path delays at converging nodes. Using analytic models to predict the means and standard deviations of gate delays as polynomial functions of the device sizes, we create a simple, computationally efficient heuristic for uncertainty-aware sizing of digital circuits via geometric programming. Monte-Carlo simulations on custom 32 bit adders and ISCAS'85 benchmarks show that about 10 % to 20 % delay reduction over deterministic sizing methods can be achieved, without any additional cost in area.

关键词： design methodology Robustness digital circuits Delay CMOS technology Uncertainty CMOS process CMOS logic circuits Circuit optimization Solid modeling

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Microfabrication and characterization of evolutionary MEMS resonators

Microfabrication and characterization of evolutionary MEMS r...

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International symposium on Micromechatronics and human Science (MHS)

作者： R. Kamalian Ying Zhang A.M. Agogino Faculty of Design Kyushu University Fukuoka Japan Department of Mechanical Engineering University of California Berkeley Berkeley CA USA

Microelectromechanical resonators have been fabricated using the MUMPs process, and characterized. The results of this characterization study are used to provide valuable feedback to improve our MEMS design tool based on the use of evolutionary synthesis algorithms known as genetic algorithms. This tool automatically generates designs that meet the user's performance goals and design constraints. To provide the necessary material property and fabrication parameters required to predict design performance, test designs for a range of performance goals and constraint settings were fabricated and characterized. We report the results of this characterization and validation experiment. design characteristics that lead to accurate performance prediction are identified and the causes for inaccurate modeling are also discussed

关键词： Micromechanical devices Fabrication Algorithm design and analysis Testing Material properties Leg Resonant frequency Predictive models Geometry Resonance

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design, simulation and synthesis of a 32-bit math-processor

Design, simulation and synthesis of a 32-bit math-processor

引用

Midwest symposium on Circuits and Systems (MWSCAS)

作者： S. Ardalan A. Adibi Electrical and Computer Engineering Department University of Waterloo Waterloo Canada Electrical Engineering Department Amirkabir University of Technology슠 Tehran Iran

This paper presented the design and results of simulation and synthesis of a 32-bit math-processor. The emphasis was placed on implementation of floating-point arithmetic unit. This math-processor is designed in fully behavioral level by using VHDL and is able to perform floating-point operation on double precision. Also as nature of behavioral description, it is easy to convert the precision to 64-bit or more. The main ALU includes four separate ALUs: sign ALU, integer number ALU, mantissa and exponent ALU (for real number). This processor uses the micro-controlling method for control unit. This behavioral design is synthesis-able and ready for layout and fabrication or FPGA based digital circuits. Synthesis was done by Leonardo Exemplar tool and it shows this design includes 27000 standard cells and can work on 40 MHz clock in 1mum CMOS technology

关键词： Computational modeling Hardware Computer simulation Circuit synthesis CMOS technology Computer aided instruction Central Processing Unit design engineering Floating-point arithmetic Fabrication

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