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检索条件"任意字段=Digital Human Modeling for Design and Engineering Symposium"

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A comparative study on the re-documentation of existing software: code annotations vs. drawing editors

A comparative study on the re-documentation of existing soft...

引用

International symposium on Empirical Software engineering (ISESE)

作者： M. Torchiano F. Ricca P. Tonella Politecnico di Torino Italy ITC IRST Trento Italy

During software evolution, programmers spend a lot of time and effort in the comprehension of the internal code structure. Such an activity is often required because the available documentation is not aligned with the implementation, if not missing at all. In order to avoid wasting the time devoted to this activity, programmers can record the knowledge they have gained in the form of multiple, structural views that address the specific aspects of the system that they have considered. Re-documentation of existing software through design views can be achieved either using a drawing editor or annotating the source code. In the first case, diagrams are produced interactively, starting from the reverse engineered information. In the second case, diagrams are produced by an annotation processing tool. Most of current reverse engineering tools fall into the first case but they have serious limitations in the information they can recover automatically and they eventually require human intervention. The aim of the empirical work reported in this paper is the comparison of these two approaches, in order to understand which is easier to use and which the current limitations of both of them are

关键词： Programming profession Documentation Reverse engineering humans Data mining Software design engineering drawings Usability Unified modeling language Investments

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Numerical human model to predict side impact thoracic trauma

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IUTAM symposium on Impact Biomechanics: From Fundamental Insights to Applications

作者： Forbes, P.A. Cronin, D.S. Deng, Y.C. Boismenu, M. Department of Mechanical Engineering University of Waterloo 200 University Ave. W. Waterloo ON N2L 3G1 Canada General Motors Corporation 6440 E.12 Mile Road Warren MI 48090-9000 United States General Motors of Canada Limited 1908 Colonel Sam Drive Oshawa ON L1H 8P7 Canada

ISBN: (纸本)1402037953

A previously developed thoracic numerical model was further enhanced for use in predicting thoracic trauma in auto crash simulations. The model consists of a detailed thoracic cage and organs developed from digital images. The first iteration of the detailed thoracic model incorporated three-dimensional finite element representations of the spine, ribs, heart, lungs and major blood vessels. The second iteration of the model was expanded to include rib cage surface muscles and upper limbs, with improvements to several material models. This detailed thoracic model correlated well with existing front and side pendulum impact experiment data. As this model will be integrated with numerical vehicle models it was necessary to develop a simplified head, pelvis, abdomen and legs. The current version of the model was developed and evaluated in a stepwise fashion using existing experimental data including frontal and side thoracic pendulum impact tests. Side abdominal and pelvic pendulum impact tests were used to design simplified representations of the associated components to complete the human body model. Complex loading via side sled impact tests was then investigated, where the body is loaded unbelted using a representative NHTSA-type and WSU-type sled test system. The predicted model response shows good agreement with the experimental data. © 2005 Springer.

关键词： Finite element method

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Power and delay analysis of 4:2 compressor cells

Power and delay analysis of 4:2 compressor cells

引用

IEEE International symposium on Circuits and Systems (ISCAS)

作者： G.M. Howard P. Mokrian M. Ahmadi W.C. Miller Research Centre for Integrated Microsystems Department of Electrical and Computer Engineering University of Windsor Windsor ONT Canada

Several low power and high speed 4:2 compressor designs of various digital logic styles are studied in this paper. HSPICE simulation results are provided giving a clear picture of the performance of these circuits in terms of power dissipation and delay. To carry out the analysis, a methodology for proper power measurement of pass-logic circuits has been developed and is presented. Finally, recommendations are made as per which circuits are most suitable depending on the needs of the system in which they will be implemented.

关键词： Delay CMOS logic circuits Adders Energy consumption Circuit simulation Arithmetic Counting circuits CMOS technology Logic design Computational modeling

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Product metrics for automatic identification of "bad smell" design problems in Java source-code

Product metrics for automatic identification of "bad smell" ...

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International symposium on Software Metrics

作者： M.J. Munro École de Technologie Supérieure (ETS)

Refactoring can have a direct influence on reducing the cost of software maintenance through changing the internal structure of the source-code to improve the overall design that helps the present and future programmers evolve and understand a system. Bad smells are a set of design problems with refactoring identified as a solution. Locating these bad smells has been described as more a human intuition than an exact science. This paper addresses the issue of identifying the characteristics of a bad smell through the use of a set of software metrics. Then by using a pre-defined set of interpretation rules to interpret the software metric results applied to Java source-code, the software engineer can be provided with significant guidance as to the location of bad smells. These issues are addressed in a number of ways. Firstly, a precise definition of bad smells is given from the informal descriptions given by the originators Fowler and Beck. The characteristics of the bad smells have been used to define a set of measurements and interpretation rules for a subset of the bad smells. A prototype tool has been implemented to enable the evaluation of the interpretation rules in two case studies

关键词： Productivity Costs State estimation Software engineering Project management Context modeling Multidimensional systems Solid modeling Process planning Geometry

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Improved fault emulation for synchronous sequential circuits

Improved fault emulation for synchronous sequential circuits

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Euromicro symposium on digital System design

作者： J. Raik P. Ellervee V. Tihhomirov R. Ubar Department of Computer Engineering Tallinn University of Technology Tallina Estonia

Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required.

关键词： Circuit faults Emulation Sequential circuits Circuit testing Circuit simulation Hardware Field programmable gate arrays Computational modeling Test pattern generators Costs

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A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switche...

引用

IEEE International symposium on Circuits and Systems (ISCAS)

作者： Hsin-Hung Ou Bin-Da Liu Department of Electrical Engineering National Cheng Kung University Tainan Taiwan

ISBN: (纸本)0780388348

This paper exploits the possibility to merge an operational amplifier-sharing technique into a switched-operational amplifier configuration. In a switched-operational amplifier based design, the capacitors connected to the operational amplifier output are not switchable, therefore the insertion of the operational amplifier-sharing technique demands two output stages within an operational amplifier. A 1-V 9-bit 2.5-Msample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 /spl mu/m CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.

关键词： Switches Voltage Analog-digital conversion Clocks Energy consumption digital-analog conversion Capacitors CMOS process Semiconductor device modeling Dynamic range

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Frequency domain system identification of a large segmented space reflector (37/sup th/ Southeastern symposium on System Theory)

Frequency domain system identification of a large segmented ...

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Southeastern symposium on System Theory

作者： E.A. Velazquez B. Dua H.R. Boussalis K. Rad SPACE Laboratory California State University Los Angeles CA USA

The NASA sponsored structures pointing and controls engineering (SPACE) testbed at CSULA is an experimental apparatus that is capable of performing experiments that simulate the complex dynamics of a large segmented optical system (James Webb Space Telescope). It is intended to serve as a generic experimental facility that can address in an integrated way the problems associated with control and structure interaction, distributed control of multi-input multi-output systems, optics, electronics, actuator and sensor design, and digital implementation. System identification experiments, aimed at achieving an accurate system model, would aid in the design of precision control techniques to satisfy the strict control requirements for this complex flexible structure. This paper describes an iterative, offline, frequency-domain, and data fit approach for estimation of a mathematical model of this complex MIMO flexible structure. Black-box parameterization of the MIMO system is achieved by modeling the input-output relationships within the system as LTI ordinary nth-order difference equations. In a multi-band approach, nonlinear least-squares optimization would provide the solution to the system parameters.

关键词： Frequency estimation Frequency domain analysis Control engineering MIMO systems Least squares methods Test facilities Flexible structures Radio astronomy

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Implementation and simulation of a cluster-based hierarchical NoC architecture for multi-processor SoC

Implementation and simulation of a cluster-based hierarchica...

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International symposium on Communications and Information Technologies (ISCIT)

作者： Xianglun Leng Ningyi Xu Feng Dong Zucheng Zhou Department of Electronic Engineering Tsinghua University Beijing China

Future high-end SoC applications will require huge computation and communication capabilities, which are provided by multiple processing cores integrated by on-chip communication architecture. Network-on-chip (NoC) provides a structured way of realizing inter-core communications on silicon for highly parallel SoC. The design of our CHNoC (cluster-based hierarchical NoC) architecture is presented, together with simulation results. It provides scalable interconnection for hundreds of cores and clusters. An MPEG-4 decoder on our architecture illustrates the performance and feasibility of CHNoC.

关键词： Network-on-a-chip Computer architecture Decoding Network topology Erbium Computational modeling Switches digital signal processing Scalability Hardware

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PROVERIFIC: experiments in employing (PSL) standard assertions in theorem-proving-based verification

PROVERIFIC: experiments in employing (PSL) standard assertio...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： P. Sule Youngsik Kim N. Mansouri Department of Electrical Engineering and Computer Science Syracuse University Syracuse NY USA

Using assertions with the design plays a central role in the design-for-verification (DFV) methodology, and hence, assertion-based design is becoming more and more widely used in industry. However, we believe that the advantages of assertions in formal verification have not been fully explored. In particular, there is little research that makes use of assertions in theorem proving. In this paper, we focus on this problem, and present our work on development of the semiautomated theorem-proving based verification system PROVERIFIC that makes use of existing design assertions. We have developed UFM, a unified modeling framework, where both the design and its assertions can be formally specified in predicate logic. Then, we defined generic predicate templates that capture the semantics of a subset of PSL assertions and a subset of Verilog within the syntax of UFM. During the verification exercise PROVERIFIC uses these templates to automatically extract formal models of a design (specified in Verilog) and its properties (specified in PSL) and translates them into higher-order logic predicates of the PVS theorem-proving system. design verification can be further conducted by proving the correctness properties in PVS. We provide examples that demonstrate the effectiveness of our theorem proving approach for verification of designs with PSL assertions.

关键词： Hardware design languages Logic design Automatic logic units Specification languages design methodology Computer industry Formal verification Monitoring digital systems Explosions

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Mixed abstraction execution for the SoftSONIC virtual hardware platform

Mixed abstraction execution for the SoftSONIC virtual hardwa...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： T. Rissa P.Y.K. Cheung W. Luk Department of Computing Imperial College London London UK Department of Electrical and Electronic Engineering Imperial College London London UK

This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity transaction level modelling (TLM) and clocked register transfer level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder

关键词： Clocks Mathematical model Computational modeling Hardware design languages Virtual prototyping Protocols Educational institutions System testing Algorithm design and analysis digital circuits

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