We propose a new approach to substrate noise modeling in early design planning of mixed-signal systems-on-chips (MS-SOCs). It can be applied to a system without any detailed knowledge (physical-layout) about its build...
详细信息
We propose a new approach to substrate noise modeling in early design planning of mixed-signal systems-on-chips (MS-SOCs). It can be applied to a system without any detailed knowledge (physical-layout) about its building blocks. We assume and justify that, in early prediction, only the most significant noise sources of substrate noise need to be considered. To capture important properties of substrate noise we consider the frequency-dependent sensitivity of analog blocks and a noise injection model for noisy digital blocks. We use experimental substrate noise simulations to build our models, and give suggestions on how to estimate noise parameters for building blocks of MS-SOC.
We describe SDL, an integrated suite of visual languages aimed at supporting the process of designing statistical surveys. SDL comprises four diagrammatic notations: survey diagrams, survey data diagrams, survey analy...
详细信息
We describe SDL, an integrated suite of visual languages aimed at supporting the process of designing statistical surveys. SDL comprises four diagrammatic notations: survey diagrams, survey data diagrams, survey analysis diagrams and survey process diagrams. A proof of concept environment supporting SDL is also presented, together with a cognitive dimensions evaluation of that environment and a cognitive walkthrough evaluation with a target end user - a professional statistician. These demonstrate the utility of SDL and lead us to propose development of a more comprehensive environment supporting the entire statistical survey process.
System interconnect modeling for high speed systems is a vital bottleneck for high speed data transfer. We demonstrate the modeling process on a high speed computer differential net running at 400 MHz (800 Mbit/s) wit...
详细信息
System interconnect modeling for high speed systems is a vital bottleneck for high speed data transfer. We demonstrate the modeling process on a high speed computer differential net running at 400 MHz (800 Mbit/s) with IBM I/O cells. The modeling of the traces on the boards was done using a field solver. The transmission line matrices were used in a SPICE model, and 3-simulation scenarios were tested for this model. The obtained EYE opening of the modeled interconnect simulation was 705 mV while the measured EYE opening for the same net topology in the laboratory was 710 mV. This shows a close match between the actual behavior and the model generated. Careful modeling can be very beneficial to get a design running at first time operation.
As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming d...
详细信息
As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat "wall" of equally critical paths, resulting in variation-sensitive designs. This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield. The method is based on adding margins on each gate delay to account for variations and using a new "soft maximum" function to combine path delays at converging nodes. Using analytic models to predict the means and standard deviations of gate delays as polynomial functions of the device sizes, we create a simple, computationally efficient heuristic for uncertainty-aware sizing of digital circuits via geometric programming. Monte-Carlo simulations on custom 32 bit adders and ISCAS'85 benchmarks show that about 10 % to 20 % delay reduction over deterministic sizing methods can be achieved, without any additional cost in area.
Microelectromechanical resonators have been fabricated using the MUMPs process, and characterized. The results of this characterization study are used to provide valuable feedback to improve our MEMS design tool based...
详细信息
Microelectromechanical resonators have been fabricated using the MUMPs process, and characterized. The results of this characterization study are used to provide valuable feedback to improve our MEMS design tool based on the use of evolutionary synthesis algorithms known as genetic algorithms. This tool automatically generates designs that meet the user's performance goals and design constraints. To provide the necessary material property and fabrication parameters required to predict design performance, test designs for a range of performance goals and constraint settings were fabricated and characterized. We report the results of this characterization and validation experiment. design characteristics that lead to accurate performance prediction are identified and the causes for inaccurate modeling are also discussed
This paper presented the design and results of simulation and synthesis of a 32-bit math-processor. The emphasis was placed on implementation of floating-point arithmetic unit. This math-processor is designed in fully...
详细信息
This paper presented the design and results of simulation and synthesis of a 32-bit math-processor. The emphasis was placed on implementation of floating-point arithmetic unit. This math-processor is designed in fully behavioral level by using VHDL and is able to perform floating-point operation on double precision. Also as nature of behavioral description, it is easy to convert the precision to 64-bit or more. The main ALU includes four separate ALUs: sign ALU, integer number ALU, mantissa and exponent ALU (for real number). This processor uses the micro-controlling method for control unit. This behavioral design is synthesis-able and ready for layout and fabrication or FPGA based digital circuits. Synthesis was done by Leonardo Exemplar tool and it shows this design includes 27000 standard cells and can work on 40 MHz clock in 1mum CMOS technology
The problem of tracking moving objects using a moving camera in real time is a complex one which requires a highly stable platform and a robust control algorithm. This paper is a continuation of our previous papers in...
详细信息
The problem of tracking moving objects using a moving camera in real time is a complex one which requires a highly stable platform and a robust control algorithm. This paper is a continuation of our previous papers in which we discussed the design and digital control routine of a 2DOF stable platform with coupled joint. In the previous paper we implemented a non-model based PI controller that proved sufficient for static targets, however for image based tracking, a number of non-linear forces are affecting the system and such scenarios require model-based controllers. The design of model based controller starts with model selection and then the estimation of its parameters. In this paper we deal with the modeling and parameters estimation of a 2 DOF platform using the least squares method.
Formal verification at system-level, which also means architecture verification, is different from functional verification at RTL level. DSP algorithms need high-level transformation to achieve optimal goals before ma...
详细信息
ISBN:
(纸本)0780388348
Formal verification at system-level, which also means architecture verification, is different from functional verification at RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping onto silicon. However, a suitable CAD tool is absent to support the simulation and verification at high-level. This paper presents a novel modeling and high-level verification methodology based on a Petri net (PN) model. By the proposed method, a DSP algorithm system in the form of FSFG (fully specified flow graph) is transformed into a PN model. Moreover, verification methods which include static and dynamical phases are applied in the PN domain. Finally, we introduce our software implementation, called HiVED, to show the experimental results.
In this paper, we propose a design of a 7 Tesla magnetic resonance imaging (MRI) whole-body coil. We describe some important features of the coil, both from a mechanical and electromagnetic perspective. We show the re...
详细信息
In this paper, we propose a design of a 7 Tesla magnetic resonance imaging (MRI) whole-body coil. We describe some important features of the coil, both from a mechanical and electromagnetic perspective. We show the results of optimizing the coil's excitation sources in a near-field phased-array manner that minimizes the standard deviation of the circularly polarized component of the transverse magnetic field, which is responsible for exciting the spins, across various cross-sections of the human body. Successful optimizations of full cross-sectional slices of the body located in the coil, as well as optimizations useful for localized imaging of a particular organ (in this case chosen to be the liver), are provided. By demonstrating the dramatic improvement in the performance of this coil utilizing the proposed complex excitation system, we show that whole-body 7 Tesla coil is physically feasible as well as probable, demonstrating great potential for future clinical and research imaging applications
Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switc...
详细信息
Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switching noise (SSN), electro magnetic interference (EMI) and crosstalk coupling. Signal integrity (SI) and timing analysis using differential drivers is computationally exhaustive due to increased complexity in design that includes features such as pre-compensation and slew rate control. Therefore, accurate macro-modeling of differential driver circuits for a quality design is a huge challenge. In this paper, a modeling technique based on recurrent neural network (RNN) is proposed to model differential driver circuits with and without pre-emphasis. Good accuracy is obtained in the test cases shown for the proposed modeling methodology at minimum computational cost.
暂无评论