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Discrete-time modeling of polynomial-based interpolation filters in rational sampling rate conversion

Discrete-time modeling of polynomial-based interpolation fil...

引用

IEEE International symposium on Circuits and Systems (ISCAS)

作者： D. Babic V. Lehtinen M. Renfors Institute of Communications Engineering Tampere University of Technology Tampere Finland

If sampling rate conversion (SRC) is performed between arbitrary sampling rates, then the SRC factor can be a ratio of two very large integers or even an irrational number. An efficient way to reduce the implementation complexity of a SRC system in those cases is to use polynomial-based interpolation filters that mimic digitally the hybrid analogue/digital system. In practice, the sampling rate conversion is approximated with a rational factor. In this case, the hybrid analogue/digital model used to represent the SRC process may be represented by an equivalent discrete-time model. The discrete-time modeling of the rational SRC has been used earlier for the zeroth order interpolation. This paper extends this idea to arbitrary polynomial-based interpolation. Furthermore, this paper derives the relation between various polynomial-based interpolation filters (Farrow structure and its modifications) and polyphase FIR model filters. This paper observes possible applications of these relations, such as filter design, implementation complexity reduction, and response distortion analysis.

关键词： Polynomials Interpolation Sampling methods Finite impulse response filter digital filters digital systems digital signal processing Arithmetic Transceivers Wireless communication

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An efficient Volterra-based behavioral model for wideband RF power amplifiers

An efficient Volterra-based behavioral model for wideband RF...

引用

Microwave, MTT-S International symposium

作者： A. Zhu M. Wren T.J. Brazil Department of Electronic and Electrical Engineering University College Dublin Ireland

Efficient and accurate behavioral modeling of RF power amplifiers with memory effects becomes of critical importance in the system-level analysis and design of wide band digital communication systems. In this paper, we present a novel Volterra-based behavioral model implemented through a bank of parallel FIR filters, the coefficients of which may be readily extracted from time-domain measurement or circuit envelope simulation. This model can reproduce the nonlinear distortion of power amplifiers with memory effects excited by wideband modulated signals with better accuracy compared to conventional quasi-memoryless models.

关键词： Radio frequency Broadband amplifiers Power amplifiers Radiofrequency amplifiers Power system modeling digital communication Finite impulse response filter Time domain analysis Distortion measurement Circuits

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Architecture design and VLSI implementation for JPEG2000

Architecture design and VLSI implementation for JPEG2000

引用

Midwest symposium on Circuits and Systems (MWSCAS)

作者： Tsung-Han Tsai Yu-Nan Pan Lian-Tsung Tsai Department of Electrical Engineering National Central University Chungli Taiwan

This paper presents an architecture design for JPEG2000 with a fast algorithm in EBCOT. The EBCOT algorithm takes advantages of resolution and SNR scalability together with a random access property, but its complexity also becomes the bottleneck of JPEG2000. In this paper, the authors proposed an architecture by using two speed-up methods. The two speed-up methods can reduce the 43% clock cycles for EBCOT context modeling. This architecture works in 40 MHz. The area of JPEG2000 is about 79787 gate counts.

关键词： Very large scale integration Discrete wavelet transforms Transform coding Image coding Clocks Context modeling Frequency domain analysis digital signal processing Computer architecture Filters

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Using integer equations for high level formal verification property checking

Using integer equations for high level formal verification p...

引用

IEEE International symposium on Quality Electronic design

作者： B. Alizadeh M.R. Kakoee Electrical and Computer Engineering University of Tehran Tehran Iran

This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verification methods use BDDs, as a low level representation of a design. BDD operations require separation of data and control parts of a design and their implementation requires large CPU time and memory. In our method; a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. This reduces the need for large BDD data structures and uses far less memory. Furthermore, this method is applied to circuits without having to separate their data and control sections. Integer equations are solved recursively by replacement and simplification operations. For this implementation, we use a canonical form of integer equations. This paper compares our results with those of the VIS verification tool that is a BDD based program.

关键词： Equations Formal verification Data structures Boolean functions Binary decision diagrams Data mining Logic design Logic circuits Flow graphs digital circuits

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Exploring storage organization in ASIP synthesis

Exploring storage organization in ASIP synthesis

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Euromicro symposium on digital System design

作者： M.K. Jain M. Balakrishnan A. Kumar Department of Computer Science and Engineering Indian Institute of Technology Delhi India

Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster. However, existing scheduler based approaches do not help in exploring storage organization. We present a scheduler based technique for exploring register file size, number of register windows and cache configurations in an integrated manner. Performances for different register file sizes are estimated by predicting the number of memory spills and its delay. The technique employed does not require explicit register assignment. The number of context switches leading to spills is estimated for evaluating the time penalty due to a limited number of register windows and cache simulator is used for estimating cache performance. The proposed technique has been validated for several benchmarks over a range of processors by comparing our estimates to the results obtained from standard simulation tools. The processors include ARM7TDMI, LEON and Trimedia (TM-1000).

关键词： Application specific processors Registers Processor scheduling Space exploration Space technology Computational modeling Application software Delay estimation Cache storage Computer science

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A digital and wide power bandwidth H-field generator for automatic test equipment

A digital and wide power bandwidth H-field generator for aut...

引用

IEEE International symposium on Defect and Fault Tolerance in VLSI Systems

作者： Fengming Zhang Y.J. Lee T. Kane L. Schiano M. Momenzadeh Y.-B. Kim F.J. Meyer F. Lombardi S. Max P. Perkinson Department of Electrical and Computer Engineering Northeastern University Boston MA USA LTX Corporation Westwood MA USA

ISBN: (纸本)0769520421

Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16 A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.

关键词： Bandwidth Power generation Automatic test equipment Solenoids Driver circuits Voltage Switches Predictive models Timing jitter design methodology

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Systolic array implementation of block based Hopfield neural network for pattern association

Systolic array implementation of block based Hopfield neural...

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IEEE Computer Society Annual symposium on VLSI

作者： Ming-Jung Seow Hau Ngo V. Asari Department of Electrical and Computer Engineering Old Dominion University Norfolk VA USA

ISBN: (纸本)0769519040

This paper suggests a systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of the Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massive parallelism and can be extended by cascading identical chips.

关键词： Systolic arrays Hopfield neural networks Neurons Computer architecture Artificial neural networks Computer networks digital circuits Parallel processing Brain modeling Biological neural networks

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An e-whiteboard application to support early design-stage sketching of UML diagrams

An e-whiteboard application to support early design-stage sk...

引用

IEEE symposium on human Centric Computing Languages and Environments

作者： Qi Chen J. Grundy J. Hosking Department of Computer Science University of Auckland Auckland New Zealand

We describe a Unified Modelling Language (UML) diagramming tool that uses an e-whiteboard, pen-based sketching interface to support collaborative design. Our tool allows designers to sketch UML visual modelling language constructs, mixing different UML diagram components, free-hand annotations and hand-written text. A key novelty of our approach is the preservation of hand-drawn diagrams and support for manipulation of the diagrams using pen-based actions. UML sketches can be "formalized" to computer-recognised and drawn diagrams, and exported to a 3rd party CASE tool.

关键词： Unified modeling language Computer aided software engineering Collaborative tools Collaborative work Computer displays Software standards Software design Application software Computer science Scheduling

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CAD for dual-V/sub th/ CMOS circuits

CAD for dual-V/sub th/ CMOS circuits

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： M. Anis Electrical and Computer Engineering Department University of Waterloo Canada

Leakage power has become one of the major obstacles to Moore's law. Unless, leakage power is lowered by orders of magnitude, we cannot enjoy the progress that technology scaling offers. Dual-V/sub th/ has emerged as an increasingly important technology that achieves very low standby leakage power, while maintaining high-performance. This paper provides a comprehensive overview of design issues related to digital integrated circuits with embedded dual-V/sub th/. It is shown that the methodology to optimally design such dual-V/sub th/ circuits must involve: (1) accurate modeling of the gate delays in the design, and (2) efficient estimation of the leakage current in every gate. The power minimization problem is then defined, taking all possible design criteria into account. The choice of the value of the threshold voltages is finally addressed.

关键词： Propagation delay Frequency Threshold voltage Logic circuits Timing Capacitance Flip-flops CMOS logic circuits Logic design design methodology

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Proceedings 2003 IEEE International symposium on Computational Intelligence in Robotics and Automation. Computational Intelligence in Robotics and Automation for the New Millennium (Cat. No.03EX694)

Proceedings 2003 IEEE International Symposium on Computation...

引用

IEEE International symposium on Computational Intelligence in Robotics and Automation (CIRA)

The following topics are dealt with: reinforcement learning; neural networks and its applications; tele-existence; fuzzy control for robots; robot assisted therapy and activity; pet-type robot for aged people's welfare; rehabilitation support system; human-robot interaction; emergence of adaptive behavior, behavior based architecture; new trends in robotics; hybrid intelligent systems in robotics; co-creation system; cooperative mobile robots; evolutionary computation; robot design; micro robot; computational intelligence in industrial applications; vision-based robotics; virtual reality; navigation system; artificial intelligence and application; fuzzy pattern recognition; intelligent systems and nonlinear control; dynamic path planning; collision detection; evolutionary robotics; modular robotics; virtual environment; global localization; pattern recognition by neural networks and evolutionary algorithms; digital human; social learning; biologically inspired robotics; manipulator analysis; manipulator control; learning from agent, human, and world; distributed autonomous systems; future manufacturing; bio-mimetric robotics; computer vision and pattern recognition; fuzzy neural network for modeling; fuzzy neural network for control; adaptive control; agent-based socio-economic simulation; intelligent method for industrial and robotics application; multi-agent systems; advanced fuzzy control; image recognition and reconstruction; sensor fusion.

关键词： Robots Intelligent control Control engineering

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