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检索条件"任意字段=Digital Human Modeling for Design and Engineering Symposium"

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Ecological driver-vehicle interface design based on situation awareness

Ecological driver-vehicle interface design based on situatio...

引用

IEEE symposium on Intelligent Vehicle

作者： Wuhong Wang Zhongjie Shen Fuguo Hou Bin Yi Department of Transportation Engineering Beijing Institute of Technology Beijing China

ISBN: (纸本)0780373464

This paper deals with the detail of identifying human factors in In-vehicle Intelligent Transport Information System (ITIS) and reveals the consequence of the effect of ITIS on driver-vehicle interface. On the basis of driving situation awareness, the ecological driver-vehicle interface analysis and optimization design for digital driving environment is performed, including the design principals, contexts and procedures. The objective is to design an ecological driver-vehicle interface with intelligent characteristics for new generation vehicle.

关键词： Vehicle driving Intelligent vehicles human factors Road vehicles Intelligent transportation systems Information systems Communication system traffic control Machine intelligence Performance analysis design optimization

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Haptic interaction for creative processes with simulated media

Haptic interaction for creative processes with simulated med...

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IEEE International Conference on Robotics and Automation (ICRA)

作者： M.C. Lin W. Baxter M. Foskey M.A. Otaduy V. Scheib Department of Computer Science University of North Carolina Chapel Hill USA

We present a survey of our recent research on the development of haptic interfaces for simulating creative processes with digital media, including 3D multiresolution modeling and 2D and 3D painting. We discuss the design issues involved and lessons learned. Based on the preliminary user studies, we observe that haptic interfaces can improve the level of usability of digital design systems and assist in capturing the feel of creative processes.

关键词： Haptic interfaces Painting Computational modeling Solid modeling Computer science Computer simulation Usability human computer interaction Auditory displays design engineering

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Logarithmic programmable preamplifier dedicated to ultrasonic receivers

Logarithmic programmable preamplifier dedicated to ultrasoni...

引用

IEEE International symposium on Circuits and Systems (ISCAS)

作者： R. Chebli A. Kassem M. Sawan PolySTIM Neurotechnology Laboratory Electrical Engineering Department Ecole Polytechnique de Montreal Canada

This paper concerns the design, the implementation and the validation of a fully integrated preamplifier dedicated to ultrasonic receivers. The preamplification technique is based on two amplification stages: a logarithmic stage called True Logarithmic Amplifier (TLA) and a programmable-gain module built around a Timing Gain Compensator (TGC). The TLA largely amplifies small amplitude signals, and moderately the large amplitude ones. However, the TGC is used to compensate signal attenuation caused by its traveling several human body tissues. Those main building blocks of an ultrasonic receiver are realized using CMOS 0.35 /spl mu/m technology. Spectre simulations of both the TLA and TGC show unity gain bandwidths of 100 MHz and 127 MHz respectively when driving a load of 1 pF. Measurements of the fabricated chip are done in our laboratory using an external digital controller programmed in FPGA. The total chip area is 7.2 mm/sup 2/ including the digital part needed to program the TGC.

关键词： Preamplifiers CMOS technology Timing Attenuation humans Biological system modeling Bandwidth Semiconductor device measurement Ultrasonic variables measurement Laboratories

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Field extraction from near field scanning for a microstrip structure

Field extraction from near field scanning for a microstrip s...

引用

IEEE International symposium on Electromagnetic Compatibility (EMC)

作者： Lin Zhang K.P. Slattery Chen Wang M. Yamaguchi K.-I. Arai R.E. DuBroff J.L. Drewnial D. Pommerenke T. Hubing Department of Electrical and Computer Engineering University of Missouri-Rolla Rolla MO USA Electromagnetic Compatibility Laboratory Department of Electrical and Computer Engineering University of Missouri Rolla Rolla MO USA Intel Desktop Architecture Lab Hillsboro OR USA Research Institute of Electrical Communication (RIEC) Tohoku University Sendai Sendai Japan Department of Electrical and Computer Engineering University of Missouri-Rolla Rolla MO

Currents associated with high-speed digital devices have significant impacts on EMI problems in VLSI design and operation. In this paper, a simple transmission line model was implemented as an initial step to represent the EMI mechanisms associated with an IC package. Numerical modeling results were compared with near field scanning measurements and show that the magnetic field deduced from the measurements agrees well with the numerical predictions.

关键词： Microstrip Numerical models Magnetic field measurement Finite difference methods Time domain analysis Integrated circuit modeling Predictive models Transmission line measurements Frequency measurement Coordinate measuring machines

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System-level modelling and implementation technique for run-time reconfigurable systems

System-level modelling and implementation technique for run-...

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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： T. Rissa M. Vasilko J. Niittylahti Institute of Digital and Computer Systems Tampere University of Technology Finland School of Design Engineering and Computing Bournemouth University UK

This paper presents a system-level approach for modelling and implementing hardware-software systems, which contain Run-Time Reconfigurable (RTR) hardware. The developed technique provides management and scheduling of RTR tasks from system-level simulations to synthesizable VHDL descriptions. The developed technique was implemented using OCAPI-xl - a system-level modelling and implementation tool based on C + + libraries. The proposed approach allows designers to explore the tradeoffs between implementation of system partitions in software, static hardware, and RTR hardware. After the system has been partitioned, an OCAPI-xl-based design flow can be utilized for implementation of all the system components.

关键词： Reconfigurable logic Hardware design languages design engineering Computational modeling Libraries Computer architecture Application specific integrated circuits Costs Energy consumption Programming

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Hierarchical face modeling and fast 3D facial expression synthesis

Hierarchical face modeling and fast 3D facial expression syn...

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Brazilian symposium on Computer Graphics and Image Processing (SIBGRAPI)

作者： Yu Zhang E.C. Prakash E. Sungt School of Electrical and Electronic Engineering Nanyang Technological University Singapore School of Electrical and Electronic Engineering Singapore School of Electrical and Electronic Engineering School of Computer Engineering Singapore School of Computer Engineering Nanyang Technological University Singapore

This paper presents a new hierarchical facial model that conforms to the human anatomy for realistic and fast 3D facial expression synthesis. The facial model has a skin/muscle/skull structure. The deformable skin model uses a kind of nonlinear spring to directly simulate the nonlinear visco-elastic behavior of soft tissue, and a new kind of edge repulsion spring is developed to prevent model collapse. The incorporation of the skull extends the scope of facial motion and facilitates facial muscle construction. The construction of facial muscles is achieved by using an efficient muscle mapping approach that ensures different muscles to be located at the anatomically correct positions. For computational efficiency, we devise an adaptive simulation algorithm which uses either a semi-implicit integration scheme or a quasi-static solver to compute the relaxation by traversing the designed data structures in a breadth-first order. The algorithm runs in real-time and has successfully synthesized realistic facial expressions.

关键词： Deformable models Skin Skull Facial muscles human anatomy Biological tissues Springs Computational efficiency Computational modeling Algorithm design and analysis

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Characterizing metastability and jitter in CMOS latch/flip-flop used as a digital mixer

Characterizing metastability and jitter in CMOS latch/flip-f...

引用

Midwest symposium on Circuits and Systems (MWSCAS)

作者： I. Shankar S.A. Morris C.G. Hutchens School of Electrical and Computer Science Engineering Oklahoma State University Stillwater OK USA

A novel low power silicon-on-insulator (SOI) CMOS digital mixer circuit that is small, fully integrable and easily implemented is presented. This circuit is for use in a microbalance counter circuit (MBC) that operates at temperatures up to 180 degrees Celsius for petroleum industry well logging applications and has a measurement acquisition time of 2.4 seconds and a frequency resolution of 59 nHz when measuring 7 MHz signals. The digital mixer circuit eliminates the need for an analog mixer and bulky, temperature sensitive low pass filter components. This paper focuses on modeling and analysis of the metastable behavior and measurement inaccuracy caused by input phase jitter of the digital mixer. There is a risk of miscount due to jitter in the input signals. This paper explains how to model this risk and generate design parameters given the user's criteria for maximum risk of count errors.

关键词： Metastasis Jitter Flip-flops Temperature sensors Frequency measurement Time measurement Latches Silicon on insulator technology CMOS digital integrated circuits Counting circuits

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Semi-formal verification of VHDL-AMS descriptions

Semi-formal verification of VHDL-AMS descriptions

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IEEE International symposium on Circuits and Systems (ISCAS)

作者： A. Salem Computer & Systems Department Faculty of Engineering Ain Shams University Cairo Egypt

In this paper a new technique for functional verification of VHDL-AMS descriptions is proposed. The technique is based on combining an equivalence checker, an analog simulator, and a term rewriting engine in a single tightly coupled verification environment. The proposed method verifies the equivalence between two VHDL-AMS architectures describing alternative implementations or different abstraction levels for the same A/MS design entity. The verification process is based on building comparator circuits for the analog outputs and miter circuits for the digital outputs. The miter circuit is verified using a novel SAT/BDD equivalence checking algorithm. The analog comparator circuit is verified using a set of rewriting rules. The equivalence of D/A & A/D converters is proved using a matching procedure.

关键词： Circuit simulation Engines Adders Computational modeling Coupling circuits Buildings Analog circuits System-on-a-chip Voltage Signal design

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Complex control of a human scale tele-operating system for micro-operation

Complex control of a human scale tele-operating system for m...

引用

IEEE International symposium on Intelligent Control (ISIC)

作者： Shuxiang Guo K. Sugimoto S. Hata Department of Intelligent Mechanical Systems EngE28099g Kagawa University Takamatsu Japan

In the medical field and in biotechnology application, a new type of human scale teleoperating system that can carry out three-dimensional high-speed micromanipulation has urgently been demanded. It is our purpose to develop a new type of human scale operating system for micro-operation that can manipulate a microobject. In this paper, we deal with a human scale teleoperating system. In order to operate microobject in human scale, the working table and micromanipulator with multiple DOF are required. So we propose a macro/micro mechanism for the system. First, we design a precision parallel micromechanism with 6-DOF (10 /spl mu/m moving range, 10 nm resolving power), and compose the macro/micro mechanism. Then, we also did the complex control for the macro/micro mechanism. The experimental results indicate that the proposed macro/micro mechanism can be controlled by teleoperation, and it is very useful for human scale micro-operation system.

关键词： Control systems humans Power system modeling Micromanipulators Force control Medical control systems Biotechnology Medical diagnostic imaging Operating systems Biomedical engineering

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SDV/sup 2/: dynamic visualization of VERILOG simulations

SDV/sup 2/: dynamic visualization of VERILOG simulations

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： R. Marczynski P.M. Seidel Computer Science and Engineering Department Southern Methodist University Dallas TX USA

Gives an introduction to SDV/sup 2/ (SMU Dynamic Verilog Visualization), a software tool for dynamic visualization of Verilog simulations currently developed at SMU. Conventional Verilog simulators focus on computing and displaying waveforms for selected signal values over time. The SDV/sup 2/ tool additionally allows to schematically visualize the module structure of a system described in Verilog and to animate signal propagations between module interfaces as dynamic transitions in the schematics. The dynamic visualization enhances conventional debugging of systems developed in Verilog hardware description language and simplifies the understanding of their dynamic behavior, which is useful both in educational and in industrial settings. In this paper we are describing the basic functionality of the SDV/sup 2/ tool and we give some insight regarding the implementation structure.

关键词： Visualization Hardware design languages Animation digital systems Computational modeling Debugging design automation Computer science Software tools Computer simulation

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