An interdisciplinary EDA research educational program was developed to enhance the application-oriented computational techniques of our computer engineering students. The goal was to broaden the scope of our EDA resea...
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ISBN:
(纸本)0780324285
An interdisciplinary EDA research educational program was developed to enhance the application-oriented computational techniques of our computer engineering students. The goal was to broaden the scope of our EDA research, which has been traditionally restricted to digital circuit designs. Innovative CAD methods developed in this program are presented and experience shared.
This paper discusses the computer-aided design of advanced control algorithms for a nuclear PWR-reactor. The implementation of the simulation model and the integration of the control methods in a typical CADCS-package...
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This paper discusses the computer-aided design of advanced control algorithms for a nuclear PWR-reactor. The implementation of the simulation model and the integration of the control methods in a typical CADCS-package are considered. The control problem may well serve as a new benchmark problem for CADCS. To evaluate the control performance of the digital control algorithms a comparison is made between classical analog PID-control and two long-range predictive control (LRPC)-methods.< >
The purpose of this paper is to summarize the research progress to date in the High-performance Computing and Simulation Research Laboratory in the area of continuously programmable digital filter systems. Topics to b...
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The purpose of this paper is to summarize the research progress to date in the High-performance Computing and Simulation Research Laboratory in the area of continuously programmable digital filter systems. Topics to be discussed include a review of digital filter algorithms, an introduction to continuously programmable digital filters, the formulation of a design and simulation environment specifically adapted for DSP system development, a discussion of microprocessor based prototype architectures proposed for optimally implementing continuously programmable digital filters in both FIR and IIR formats, and finally conclusions and research plans for the future.< >
Modern design evaluation technologies based on human figure simulations are helping us to make fuller and more accurate assessments of human/machine and workplace interfaces. As computer graphics and related digital t...
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Modern design evaluation technologies based on human figure simulations are helping us to make fuller and more accurate assessments of human/machine and workplace interfaces. As computer graphics and related digital technologies advance, one will be able to illustrate, predict, evaluate, and document a wider array of human performance issues involving system useability concurrently with design development. The design Evaluation for Personnel, Training, and human Factors (DEPTH) program is developing and integrating many of these technologies for engineering applications. This paper provides an overview of current and planned DEPTH technology developments.< >
As the number of computer tools to perform. EMI modeling tasks increase, the need for a set of standard "problems" becomes more important. These standard problems allow vendors to benchmark their codes again...
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As the number of computer tools to perform. EMI modeling tasks increase, the need for a set of standard "problems" becomes more important. These standard problems allow vendors to benchmark their codes against each other and provide the potential user with realistic examples of uses of the code applied to real world problems. This paper presents a number of different problems that exist in the real-life EMI engineer's world, and where EMI modeling could help the engineer make appropriate decisions. These problems are obtained by breaking the overall design problem into smaller subproblems, each manageable by itself. Results from the individual problems can be combined as needed.< >
Due to the complexity of Synchronous digital Hierarchy (SDH) networks, planning and developing such networks requires computer aided design tools. Because survivable SDH network design is a relatively new area and the...
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Due to the complexity of Synchronous digital Hierarchy (SDH) networks, planning and developing such networks requires computer aided design tools. Because survivable SDH network design is a relatively new area and the need for planning tools has only been recognized in the last few years, virtually no comprehensive tools exist to address the specific questions which must be answered by SDH network engineers. In particular the migration of existing networks into SDH networks requires the capability to model existing transmission and switching methodologies while simultaneously modeling new hybrid topologies consisting of meshed point to point systems, unidirectional and bidirectional topologies and direct point to point TIE lines. Two hierarchical metropolitan optical transmission network architectures examined in this paper using a simulation tool to demonstrate the requirements for a SDH network analysis tool.< >
During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a...
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ISBN:
(纸本)0780324285
During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy.
The design of a low-power digital signal processor requires an energy-driven approach to optimize the processing algorithm and hardware architecture over area, time and energy. In addition, the detailed understanding ...
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The design of a low-power digital signal processor requires an energy-driven approach to optimize the processing algorithm and hardware architecture over area, time and energy. In addition, the detailed understanding of the interactions between algorithm and architecture is crucial for the overall energy optimized system design and partitioning. To accurately characterize a system, a complete algorithm and architecture need to be simulated together over a representative set of input signals, and the simulator's speed is important. The existing academic and commercial simulation tools lack the ability to efficiently model the energy consumption of a complete system. The authors introduce OPERAS (Object-oriented Power Estimating Restructurable Architecture Simulator), an object-oriented system simulator with power estimation capability. OPERAS's design uses object-oriented principles and efficient C++ language to model and simulate the system behavior.< >
Summary form only given. A methodology for designing embedded DSP systems containing interacting hardware and software components is presented. The software typically comprises a program running on a programmable digi...
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Summary form only given. A methodology for designing embedded DSP systems containing interacting hardware and software components is presented. The software typically comprises a program running on a programmable digital signal processor and the hardware consists of the processor, custom synthesized hardware modules, and the interface between the two. The methodology allows the designer to begin with a high-level dataflow description of the algorithm and generates a simulation model as well as a synthesizeable description for the entire system. The authors have implemented this mechanism within the Ptolemy framework as a heterogeneous target called the design Assistant.< >
A program for the design of leaf cells for silicon compilers of digital VLSI circuits, is being developed. It uses rule based modules to put together basic circuits, check design rules, check designs constraints and t...
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A program for the design of leaf cells for silicon compilers of digital VLSI circuits, is being developed. It uses rule based modules to put together basic circuits, check design rules, check designs constraints and to control each of these constituent tasks. An optimization algorithm, in this case a genetic algorithm, optimizes the layout, under the control of the rule system. The program is divided into modules that can run together using a client-server model.< >
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