Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic ga...
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Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic gate to be mapped into real circuits directly, although the method needs a large number of neurons. In order to reduce the total number of neurons and computing cost, they propose a neural function called NIF, neural inverse function, for ATPG, automatic test pattern generation. A NIF is defined as a Boolean product form of sums. Simulation results of n-bit full-adder circuits show that the computational order of ATPG is approximately O(n/sup 0.5/) in parallel convergence, and O(n/sup 0.9/) in sequential. Compared with the former method, the new method is able to find a set of test patterns about n times faster than the former method, because NIF method needs a small amount of neurons.< >
A method for removing the discontinuity in Gds going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described. A detailed ana...
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A method for removing the discontinuity in Gds going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described. A detailed analysis of the problem and simulation results before and after the modification are presented.
Error diffusion is a powerful means to improve the subjective quality of a quantized image by shaping the spectrum of the display error. Considering an image in raster ordering, this is done by adding a weighted sum o...
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ISBN:
(纸本)0819408204
Error diffusion is a powerful means to improve the subjective quality of a quantized image by shaping the spectrum of the display error. Considering an image in raster ordering, this is done by adding a weighted sum of previous quantization errors to the current pixel before quantization. These weights form an error diffusion filter. In this paper a method is proposed to find an optimized error diffusion filter for image display applications. The design is based on the lowpass characteristic of the contrast sensitivity of the human visual system. The filter is chosen so that a cascade of the quantization system and the observer's visual modulation transfer function yields a whitened spectrum of error. It is shown in this paper that the optimal error diffusion filter corresponds to a linear prediction filter of the human visual transfer function. A first order linear filter for an underlying non-separable vision model is examined. The resulting images contain mostly high frequency components of the display error, which are less noticeable for the viewer. This corresponds well to previously published results about the visibility of halftoning patterns. An informal comparison with other error diffusion algorithms shows less artificial contouring and increased image quality.
This paper describes an information distribution system that merges the personal computer (PC) and facsimile technologies to enhance and expand the capabilities of existing stand-alone facsimile machines. The goal is ...
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An Information Requirements Analysis was conducted by the Armstrong Laboratory as a precursor activity to the conceptual design of missionized crew systems appropriate to the requirements of manned hypersonic flight v...
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A least-squares model-based approach to digital halftoning is proposed. It exploits both a printer model and a model for visual perception. It attempts to produce an 'optimal' halftoned reproduction, by minimi...
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ISBN:
(纸本)0819408204
A least-squares model-based approach to digital halftoning is proposed. It exploits both a printer model and a model for visual perception. It attempts to produce an 'optimal' halftoned reproduction, by minimizing the squared error between the response of the cascade of the printer and visual models to the binary image and the response of the visual model to the original gray-scale image. Conventional methods, such as clustered ordered dither, use the properties of the eye only implicitly, and resist printer distortions at the expense of spatial and gray-scale resolution. In previous work we showed that our printer model can be used to modify error diffusion to account for printer distortions. The modified error diffusion algorithm has better spatial and gray-scale resolution than conventional techniques, but produces some well known artifacts and asymmetries because it does not make use of an explicit eye model. Least-squares model-based halftoning uses explicit eye models and relies on printer models that predict distortions and exploit them to increase, rather than decrease, both spatial and gray-scale resolution. We have shown that the one-dimensional least-squares problem, in which each row or column of the image is halftoned independently, can be implemented with the Viterbi's algorithm. Unfortunately, no closed form solution can be found in two dimensions. The two-dimensional least squares solution is obtained by iterative techniques. Experiments show that least-squares model-based halftoning produces more gray levels and better spatial resolution than conventional techniques. We also show that the least- squares approach eliminates the problems associated with error diffusion. Model-based halftoning can be especially useful in transmission of high quality documents using high fidelity gray-scale image encoders. As we have shown, in such cases halftoning can be performed at the receiver, just before printing. Apart from coding efficiency, this approach permit
Describes code-level modeling in XSPICE, an extended version of the SPICE3 simulator from the University of California at Berkeley. XSPICE extends SPICE3's capabilities to allow efficient simulation of mixed-signa...
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Describes code-level modeling in XSPICE, an extended version of the SPICE3 simulator from the University of California at Berkeley. XSPICE extends SPICE3's capabilities to allow efficient simulation of mixed-signal (analog/digital) circuits and systems. XSPICE's code-level modeling approach allows new models to be easily added to the SPICE3 core, providing a practical alternative to traditional macromodeling techniques. Addition of event-driven simulation extends SPICE3 to include 12-state digitalmodeling. User-defined data types allow simulation of designs such as sampled-data filters. A library of over 40 predefined code models has been developed, covering analog, digital, and hybrid devices and functions. The complete XSPICE simulator has been integrated with the Mentor Graphics MSPICE CAE (computer-aided engineering) environment, and provides a general interprocess communication interface for connection to other CAE system software. An example illustrating the use of XSPICE in top-down, system-level design is shown. The system is a simple MIDI (musical instrument digital interface) synthesizer.< >
Summary form only given. modeling and simulation capabilities are key components ULSI design systems yet to be developed. Issues in this area revolve around the critical ability to perform efficient simulation, i.e., ...
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Summary form only given. modeling and simulation capabilities are key components ULSI design systems yet to be developed. Issues in this area revolve around the critical ability to perform efficient simulation, i.e., the simulation with the least real-time delay before acceptably accurate results are available to the design engineer in an information format. Implicit in this is the premise that there is never enough computational and information management capability to fully analyze (no approximations or truncations) real designs in times consistent with humandesignengineering practice. The exploration and definition of the boundaries between different electrical analysis domains were discussed. design data manipulation and information management, which are critical for systems involving a few dozen chips with a few thousand I/Os and a few tens of thousands of interconnect lines and which will become more of an issue when the chip I/O count and interconnect line count increase by one or two orders of magnitude, were also considered.< >
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