The author argues that the electronic design community too often tries to apply discrete event simulation technology, such as VHDL, to applications for which it is ill-suited. In particular he considers the simulation...
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The author argues that the electronic design community too often tries to apply discrete event simulation technology, such as VHDL, to applications for which it is ill-suited. In particular he considers the simulation of synchronous digitaldesigns, and reports two orders of magnitude speed improvement by using compiled simulation instead. The basic design of a simple compiled simulator is outlined.< >
Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structur...
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Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately scheduling coroutines corresponding to the design entities. The behavioral and structural description is translated into coroutines by compiling IDEAL data transfer and control constructs into 'C'. The semantics of IDEAL constructs are discussed and the simulator implementation and supporting environment are described.< >
In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diag...
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In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms.< >
An analog VLSI processor for motion computation is presented. It is based on the Hassenstein-Reichardt-Poggio model for information processing in the visual system of the fly. The authors show how neural network model...
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An analog VLSI processor for motion computation is presented. It is based on the Hassenstein-Reichardt-Poggio model for information processing in the visual system of the fly. The authors show how neural network models can be mapped on silicon integrated circuits for performing tasks that can not be handled efficiently by digital computing machinery. The design is based on current-mode subthreshold MOS circuits using device-level design and exploiting the translinear property of the MOS transistor. Experimental results from fabricated chips are presented.< >
The author presents the first comprehensive study of fault modeling of the class of sample-and-hold circuits frequently used in mixed analog/digital signal processors. The faults under study consist of catastrophic fa...
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The author presents the first comprehensive study of fault modeling of the class of sample-and-hold circuits frequently used in mixed analog/digital signal processors. The faults under study consist of catastrophic faults and out-of-specification faults. Even if the faults are restricted to the passive components and MOS switches (i.e. the operational amplifiers are assumed fault-free), the effects of these faults are quite complex, especially the out-of-specification faults. For example, an incorrect value of the resistor R/sub on/ of an MOS switch and an incorrect value of the capacitor in some cases have the same faulty manifestations at the output, and may be thought of as equivalent faults. The concept of fault equivalence is validated for analog circuits. The results show that various types of faults are distinguishable, thus reducing the size of the analog fault dictionary used in further diagnosis.< >
The authors present an accurate physical timing model for large bipolar emitter-coupled-logic (ECL) circuits. A delay model is derived based on device equations and average branch current analysis, and no exhaustive p...
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The authors present an accurate physical timing model for large bipolar emitter-coupled-logic (ECL) circuits. A delay model is derived based on device equations and average branch current analysis, and no exhaustive preprocessing or table interpolation is required. The dynamic fanout effects of the ECL circuits can be incorporated by an accurate fanout modeling approach combined with an effective fanout collapsing technique. In addition, the use of a parametric correction scheme permits greater freedom in handling complex delay-sensitive effects such as high-level injection and bipolar parasitic resistances than would otherwise be possible. This delay model with input waveform effects provides delay estimates that are typically within 10% of SPICE estimates.< >
Use of two-dimensional process and device simulators in predicting the latch-up immunity of a BiCMOS process is described. Recent advances have resulted in the availability of a number of simulation tools such as PISC...
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Use of two-dimensional process and device simulators in predicting the latch-up immunity of a BiCMOS process is described. Recent advances have resulted in the availability of a number of simulation tools such as PISCES in the device simulation area and others such as SUPRA and SUPREM-2, -3, and -4 in the process simulation area. SUPRA was used for process modeling, and PISCES-2B for device simulations. It is shown that despite SUPRA's limitations and restrictions in the sequential choice of process steps, with tricks and some help from one-dimensional SUPREM-3 results, satisfactory 2-D profiles can be obtained. Therefore, PISCES-2B receives a two-dimensional device structure with no manual interference. It is shown that the models developed yield not only the MOSFET characteristics but also the parasitic transistors gains. Results obtained from the simulation of the device under latch-up test conditions help the engineer to design latch-up-free CMOS and BiCMOS processes.< >
STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits which conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical c...
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STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits which conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solver unit for dynamic integration of analytical model equations across hierarchical boundaries. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via successive solution refinement. Multilevel models of increasing sophistication are used by scan and optimization modules to home-in on a global optimal solution. design experiments have shown that STAIC can produce satisfactory results.< >
An approach to automatic generation of symbolic models relating a digital cell delay to CMOS transistor dimensions is proposed and used for deterministic and statistical delay optimization in combinational CMOS VLSI c...
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An approach to automatic generation of symbolic models relating a digital cell delay to CMOS transistor dimensions is proposed and used for deterministic and statistical delay optimization in combinational CMOS VLSI circuits. The models used provide about 5% accuracy with respect to the SPICE-3 circuit simulator, but are up to 5 to 6 orders of magnitude faster. A first order statistical device model is introduced. Examples of optimization of several VLSI circuits are shown, the largest being composed of about 1200 transistors, with 380 gate widths and 10 different active delay paths optimized in 308 CPU seconds. A generic optimization system, able to perform the relevant deterministic and statistical optimization tasks, is described.< >
A fast recursive convolution for the precise digital simulation of imperfect lenses and motion blurring of scanning detectors was invented for the production of large sets of human and Automatic Target Recognizer (ATR...
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ISBN:
(纸本)0819403601
A fast recursive convolution for the precise digital simulation of imperfect lenses and motion blurring of scanning detectors was invented for the production of large sets of human and Automatic Target Recognizer (ATR) test imagery. The method shows a wide range of other possible applications. A robust algorithm for image segmentation, the explanation of horizontal-vertical preference and high periodicity acuity in the human visual system might emerge.
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