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检索条件"任意字段=Distributed Memory Computing Conference"

共 8890 条记录，以下是31-40 订阅

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MoC-System: Efficient Fault Tolerance for Sparse Mixture-of-Experts Model Training 25

MoC-System: Efficient Fault Tolerance for Sparse Mixture-of-...

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30th ACM International conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2025

作者： Cai, Weilin Qin, Le Huang, Jiayi Guangzhou China

ISBN: (纸本)9798400710797

As large language models continue to scale up, distributed training systems have expanded beyond 10k nodes, intensifying the importance of fault tolerance. Checkpoint has emerged as the predominant fault tolerance strategy, with extensive studies dedicated to optimizing its efficiency. However, the advent of the sparse Mixture-of-Experts (MoE) model presents new challenges due to the substantial increase in model size, despite comparable computational demands to dense models. In this work, we propose the Mixture-of-Checkpoint System (MoC-System) to orchestrate the vast array of checkpoint shards produced in distributed training systems. MoC-System features a novel Partial Experts Checkpointing (PEC) mechanism, an algorithm-system co-design that strategically saves a selected subset of experts, effectively reducing the MoE checkpoint size to levels comparable with dense models. Incorporating hybrid parallel strategies, MoC-System involves fully sharded checkpointing strategies to evenly distribute the workload across distributed ranks. Furthermore, MoC-System introduces a two-level checkpointing management method that asynchronously handles in-memory snapshots and persistence processes. We build MoC-System upon the Megatron-DeepSpeed framework, achieving up to a 98.9% reduction in overhead for each checkpointing process compared to the original method, during MoE model training with ZeRO-2 data parallelism and expert parallelism. Additionally, extensive empirical analyses substantiate that our methods enhance efficiency while maintaining comparable model accuracy, even achieving an average accuracy increase of 1.08% on downstream tasks. © 2025 ACM.

关键词： memory management

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19th International conference on Hybrid Artificial Intelligence Systems, HAIS 2024

19th International Conference on Hybrid Artificial Intellige...

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19th International conference on Hybrid Artificial Intelligence Systems, HAIS 2024

ISBN: (纸本)9783031741852

The proceedings contain 52 papers. The special focus in this conference is on Hybrid Artificial Intelligence Systems. The topics include: The Third Codon Nucleotide’s Role in Genetic Recombination Within SARS-CoV-2 Spike Protein: A Pilot Study;machine Learning for the Identification of Biomarker and Risk Factors associated with Depression in Adult Population: Preliminary Results on a Small Cohort;Unveiling HIV-1 U Sequences: Shedding Light Through Transfer Learning on Genomic Spectrograms;model to Early Detection of Autism Spectrum Disorder Through Opinion Mining Approach;A Short Analysis of Hybrid Approaches in COVID‑19 for Detection and Diagnosing;A Graph Neural Network with Multi-head Attention for Universal Brain Disease Diagnosis from fMRI Images;a Computer Vision Approach to Detect Facial Characteristics Related to Encephalopathy in Term Infants;SPADE Norms: a distributed General Framework for Normative Multi-agent Systems;Finding Optimal Classroom Arrangements to Minimize Cheating in Exams Using a Hybrid AI System;resilience to the Flowing Unknown: An Open Set Recognition Framework for Data Streams;a Comparison Procedure for the Evaluation of Metaheuristics;Nyström and RFF Ensembles for Large-Scale Kernel Predictions;application of Transfer Learning to Online Models in Malware Detection;a New Training Algorithm for Support Vector Machines;soft Adaptive Segments for Bio-Inspired Temporal memory;assessing Generative Artificial Intelligence in Fundamental Physics with Gaussian Processes;implementation of Classical Decision Trees in a Quantum computing Paradigm;machine Learning Methods as Robust Quantum Noise Estimators;The Impact of Data Annotations on the Performance of Object Detection Models in Icon Detection for GUI Images;bayesian Model Selection Pruning in Predictive Maintenance;neonates Crying Detection Through Feature Extraction and Machine Learning Methods;differentiable Prototypes with distributed memory Network for Continual Learning;efficient Continu

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19th International conference on Hybrid Artificial Intelligence Systems, HAIS 2024

19th International Conference on Hybrid Artificial Intellige...

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19th International conference on Hybrid Artificial Intelligence Systems, HAIS 2024

ISBN: (纸本)9783031741821

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A Prompt Chaining Framework for Long-Term Recall in LLM-Powered Intelligent Assistant 25

A Prompt Chaining Framework for Long-Term Recall in LLM-Powe...

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30th International conference on Intelligent User Interfaces, IUI 2025

作者： Seo, Seongbum Yoo, Sangbong Jang, Yun Sejong University Seoul Korea Republic of

ISBN: (纸本)9798400713064

Intelligent Assistants (IAs) often struggle with maintaining context in extended conversations, limiting their long-term recall capabilities and personalization. This study introduces a prompt chaining framework that integrates Large Language Models (LLMs) into IAs to address these issues. Our approach encompasses: (1) a formative study (N=30) analyzing IA-user interactions and identifying key challenges in long-term memory and personalization, (2) development of an LLM-based system with a novel prompt chaining mechanism for improved context retention, adaptable to various LLM architectures, and (3) implementation of a multi-step reasoning process to enhance context-aware and personalized responses. We evaluated the framework through quantitative analysis on multiple datasets, tested with different LLM backends, and conducted ablation studies to assess component contributions. The results show improvements in long-term recall, context awareness, and personalization across all tested models and datasets. A human evaluation study (N=47) indicated better Sensibleness, Consistency, and Personalization in IA response. This approach enhances IA memory capabilities and can adapt to different LLM backends. © 2025 Copyright held by the owner/author(s).

关键词： memory architecture

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Improved GPU memory Management in Evolutionary Decision Tree Induction for Large-Scale Data 15th

Improved GPU Memory Management in Evolutionary Decision Tre...

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15th International conference on Parallel Processing and Applied Mathematics, PPAM 2024

作者： Jurczuk, Krzysztof Reska, Daniel Czajkowski, Marcin Kretowski, Marek Faculty of Computer Science Bialystok University of Technology Wiejska 45a Bialystok15-351 Poland

ISBN: (纸本)9783031856969

Decision trees (DTs) are explainable machine learning techniques applicable to classification and regression problems. Traditionally, DTs are built through a top-down greedy search, which is usually fast but may lead to sub-optimal solutions. An alternative approach involves the use of evolutionary algorithms (EAs), which allow for more global exploration that can yield simpler and accurate DTs. However, the EA-based DT induction is computationally demanding, especially for large-scale data. To alleviate these high computing requirements, various parallel and distributed accelerations are continuously explored. In this paper, we focus on a GPU-supported solution and extend it by improving memory management. To reduce synchronization points between GPU threads (both within and across blocks), the new solution avoids atomic functions. However, such an approach requires allocating individual result buffers for each thread, which increases memory requirements. To compensate for this, a compact in-memory representation of DTs is additionally applied. Moreover, an additional level of reduction is necessary. Experimental validation on various datasets, both artificial and real-life, shows that the enhanced solution further accelerates the EA-based DT induction. The results also reveal that the time savings increase as the dataset size grows and are influenced by DT size. Therefore, the hybrid solution provides the best time results, by applying synchronization avoidance for smaller DTs and the opposite strategy for larger ones. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： memory management

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On development of a pervasive computing aided assistive systems for the elderly in Internet of Things 2

On development of a pervasive computing aided assistive syst...

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2nd International conference on Big Data, Computational Intelligence, and Applications, BDCIA 2024

作者： Yao, Di Xing, Yutao Luo, Chenyao Song, Huaju Beijing100083 China School of Electronic and Optical Engineering Nanjing University of Science and Technology Nanjing210094 China Portland Institute Nanjing University of Posts and Telecommunications Nanjing210003 China School of Environmental Science Nanjing XiaoZhuang University Nanjing210017 China

ISBN: (纸本)9781510689053

With the rapid development of sensors, wireless communication, and computing technology, Internet of Things (IoT) has gained significant research interest. In particular, increasing people-oriented applications and systems have been developed to improve the quality of life with intelligent services. In this paper, we propose a situational awareness system based on pervasive computing. In response to the current situation of a large number of elderly people living alone or lacking care, an intelligent assistance system model for elderly people living alone is proposed, aiming to solve problems such as forgetting to turn off lights caused by memory decline, falls caused by mobility impairment, and loss of dementia elderly people. Furthermore, we adopt the OSGi architecture to implement the proposed system. In addition, a virtual device module is designed to shield underlying device heterogeneity ensuring seamless collaboration between devices and services. To further enhance the system's capabilities, optical sensors are integrated for intelligent health monitoring, enabling real-time tracking of vital signs such as heart rate and respiratory rate, as well as early detection of potential health anomalies. To make services transparent to users, we explore the integration methods of distributed sensors and intelligent devices in pervasive computing environments. Experimental results indicate that the system can effectively improve the comfort and safety of elderly people's lives, enhance the convenience of daily affairs and risk prevention and control capabilities. Therefore, the developed system not only provides a technical framework for intelligent assistance systems for the elderly, but also has significant implications for the application of pervasive computing in the field of social welfare. © 2025 SPIE.

关键词： Assistive technology

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R-HLS: An IR for Dynamic High-Level Synthesis and memory Disambiguation based on Regions and State Edges 24

R-HLS: An IR for Dynamic High-Level Synthesis and Memory Dis...

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43rd International conference on Computer-Aided Design, ICCAD 2024

作者： Metz, David Reissmann, Nico Själander, Magnus Norway

ISBN: (纸本)9798400710773

Dynamically scheduled hardware enables high-level synthesis (HLS) for applications with irregular control flow and latencies, which perform poorly with conventional statically scheduled approaches. Since dynamically scheduled hardware is inherently data flow based, it is beneficial to have an intermediate representation (IR) that captures the global data flow to enable easier transformations. State-of-the-art dynamic HLS utilize control flow based IRs, which model data flow only at the basic block level, requiring the rediscovery of inter-block parallelism. The Regionalized Value State Dependence Graph (RVSDG) is an IR that models (1) control flow as part of the global data flow utilizing regions and (2) memory dependencies using state edges. We propose R-HLS, a new RVSDG dialect targeted for dynamic high-level synthesis. R-HLS explicitly models control flow decisions, routing, and memory, which are only abstractly represented in the RVSDG. Expressing the control flow as part of the data flow reduces the need for complex optimizations to extract performance and enables easy conversion to parallel circuits. Furthermore, we present a distributed memory disambiguation optimization that leverages memory state edges to decouple address generation from data accesses, resulting in resource efficient out-of-program-order execution of memory operations. Our results show that R-HLS effectively exposes parallelism, resulting in fewer executed cycles and a 10% speedup on average, compared to the state-of-the-art in dynamic HLS with optimized memory disambiguation. These results are achieved with a significant reduction in resource utilization, such as a 79% reduction in lookup-tables and 22% reduction in flip-flops, on average. © 2024 Copyright is held by the owner/author(s).

关键词： Table lookup

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AsymFB: Accelerating LLM Training Through Asymmetric Model Parallelism 20th

AsymFB: Accelerating LLM Training Through Asymmetric Model P...

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20th IFIP WG 10.3 International conference on Network and Parallel computing, NPC 2024

作者： Zhang, Jiawei Shao, En Wang, Leping Tan, Guangming Sun, Ninghui Institution of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9789819628292

Transformer-based large language models (LLMs) have become a dominant force in natural language processing, advancing both research and industry. As model sizes have grown from billions to hundreds of billions of parameters, training them on a single GPU is no longer feasible, making distributed training essential. Existing distributed training methods partition models into non-overlapping segments of equal-size to cut memory usage on each device, but this creates cross-device data dependencies. These dependencies lead to delays and reduced throughput, particularly during the forward phase. This paper introduces AsymFB, a novel model parallelism algorithm designed to address these limitations. By adopting an asymmetric partitioning approach, AsymFB assigns varying numbers of devices to different training phases—forward, recompute, and backward—optimizing resource allocation and minimizing performance penalties. Our approach demonstrates up to a 1.25× speedup compared to traditional methods, significantly improving the efficiency of training large-scale LLMs and mitigating common performance bottlenecks. © IFIP International Federation for Information Processing 2025.

关键词： Resource allocation

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A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable computing with Direct Die-to-Yarn Integration of 0.6×2.15mm2SoC and bySPI Chiplets 72

A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wea...

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72nd IEEE International Solid-State Circuits conference, ISSCC 2025

作者： Agrawal, Anjali Chen, Zhenghong Desman, Braden E. Wang, Jinhua Tanaka, Akiyoshi Foysal, Fahim Hess, Charlie D. Farrell, Will Owens, Jim Truesdell, Daniel S. Calhoun, Benton H. University of Virginia CharlottesvilleVA United States Nautilus Defense LLC PawtucketRI United States

ISBN: (纸本)9798331541019

This paper proposes a scalable, 2-dimensional network-on-textiles (kNOT) comprised of systems-on-chip (SoCs) and 'bySPI' networking chiplets that are jointly capable of supporting heterogeneous programming, multiple sensing modalities, and a distributed memory system. Emerging e-textiles must retain the flexibility and comfort of their host garment to be viable in wearable applications for healthcare, virtual reality, and sports [1]-[4]. Prior integration efforts have demonstrated textile computing by weaving flexible filament circuits [5]-[7], embroidering conductive yarns [8], and fabricating electronic fibers [9]-[10]. Still, these works suffer from a combination of bulky, rigid components, high cost, or 1-dimensionality (Fig. 37.2.1). To preserve the textile's look and feel, SoCs for fabric integration must also be highly miniaturized, feature minimal area-hungry IO interfaces, be easily programmable, and be fully integrable. The e-textile system in [11] integrated a health sensing chip onto a planar fashionable circuit board, yet the board (25×25mm2) is 40× larger than the chip itself. The System-in-Fiber from [12] is fully autonomous but has many IO pads, is limited to 1D networks, and requires an interposer (4.7×3.7mm2) that is 3.8× larger than the die. Most recently, a battery-less e-textile system in [13] integrates cm-scale harvesting tiles and an inductor onto a shirt, but it lacks an integrated SoC. Many wearable applications also demand substantial on-garment storage, yet large memories are unsuited for comfortable textile integration due to their sizable footprint. Our kNOT solution addresses this by replacing monolithic memory units with a distributed set of smaller memories. However, networking these chiplets via existing bus standards incurs significant area and power penalties [14]. Existing Body Area Networks highlight the potential of multi-chip solutions, but they lack seamless textile integration [15]-[17]. Hence, to truly realize a fabric comp

关键词： Network-on-chip

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Towards Optimizing Cost and Performance for Parallel Workloads in Cloud computing

Towards Optimizing Cost and Performance for Parallel Workloa...

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15th International conference on Cloud computing and Services Science, CLOSER 2025

作者： Maas, William Rossi, Fábio Diniz Luizelli, Marcelo C. Navaux, Philippe O.A. Lorenzon, Arthur F. Institute of Informatics Federal University of Rio Grande do Sul Brazil Federal Institute Farroupilha Campus Alegrete Brazil Federal University of Pampa Campus Alegrete Brazil

ISBN: (纸本)9789897587474

The growing popularity of data-intensive applications in cloud computing necessitates a cost-effective approach to harnessing distributed processing capabilities. However, the wide variety of instance types and configurations available can lead to substantial costs if not selected based on the parallel workload requirements, such as CPU and memory usage and thread scalability. This situation underscores the need for scalable and economical infrastructure that effectively balances parallel workloads’ performance and expenses. To tackle this issue, this paper comprehensively analyzes performance, costs, and trade-offs across 18 parallel workloads utilizing 52 high-performance computing (HPC) optimized instances from three leading cloud providers. Our findings reveal that no single instance type can simultaneously offer the best performance and the lowest costs across all workloads. Instances that excel in performance do not always provide the best cost efficiency, while the most affordable options often struggle to deliver adequate performance. Moreover, we demonstrate that by customizing instance selection to meet the specific needs of each workload, users can achieve up to 81.2% higher performance and reduce costs by 95.5% compared to using a single instance type for every workload. Copyright © 2025 by SCITEPRESS - Science and Technology Publications, Lda.

关键词： Parallel processing systems

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