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BA-BNN: Detect LDoS Attacks in SDN based on Bat Algorithm and BP Neural network

BA-BNN: Detect LDoS Attacks in SDN Based on Bat Algorithm an...

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IEEE International conference on Big Data and Cloud Computing (BdCloud)

作者： Xinmeng Li Nengguang Luo Dan Tang Zhiqing Zheng Zheng Qin Xinxiang Gao College of Computer Science and Electronic Engineering (CSEE) Hunan University Hunan China

Low-rate Denial of Service (LDoS) attack is a novel form of the denial-of-service attack. Consequently, there is something difficult to detect it by conventional attack detection techniques. BP neural network detects LDoS attacks is feasible because of its features such as high non-linear. However, it also has the defects such as poor global search ability. Bat algorithm that has the strong global search ability can make up those defects. We proposed a LDoS attack detection method that is on account of Bat Algorithm and BP Neural network (BA-BNN). For the sake of making a verification on how valid our method is, a series of LDoS attack experiments were carried out in a virtual Software Defined network (SDN) composed of Mininet emulator and Ryu controller, obtaining the TCP and UDP traffic data. We use the algorithm called random forest to select characteristics of training data for BP neural network ameliorated by an intelligent algorithm, Bat algorithm, and construct the LDoS attack detection model. We compare our method with some other methods. The results show that the method we adopt is a highly accurate LDoS attack detection method. It has higher correct rate and detection rate, and lower false negative rate and false positive rate.

关键词： Neural networks Software algorithms Training data Denial-of-service attack Feature extraction Data models Software defined networking

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A Two-level Concurrent Address Translation Cache of High Performance Interconnect network

A Two-level Concurrent Address Translation Cache of High Per...

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IEEE International conference on Big Data and Cloud Computing (BdCloud)

作者： Jianmin Zhang Tiejun Li Yan Sun College of Computer National University of Defense Technology Changsha China

Most of users are accustomed to utilize the virtual address in their parallel programs running at the exascale computer systems. Therefore the virtual and physical address translation mechanism is necessary and crucial to bridge the hardware interface and software application. We proposed a novel two-level concurrent address translation Cache (TLC) for high performance interconnect network–TH Express-2. The TLC is composed of L1 Cache (L1C) and main eDRAM-based Cache (MEC). A fast and small L1 Cache implemented by high-speed SRAM is adopted. The MEC employs the large capacity eDRAM (embedded Dynamic Random Access Memory) macros to meet the high hit ratio requirement. To avoid the stall incurring by refresh collision, a novel eDRAM stall-hidden refreshing algorithm is proposed. Many tests have been conducted on the real chip implementing TLC. The results show that the MEC has high hit ratio and L1C has considerable hit ratio while running the well-known benchmarks. Owing to the L1 Cache involved, the total runtime of TLC is reduced about 14%, only at the cost of 1.2% area occupied.

关键词： Bridges Runtime Costs Heuristic algorithms Random access memory Benchmark testing Software

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A Modified Cascaded Feed Froward Neural network distributed Denial of Service Attack Detection using Improved Regression based Machine Leaning Approach 6

A Modified Cascaded Feed Froward Neural Network Distributed ...

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6th International conference on Trends in Electronics and Informatics (ICOEI)

作者： Mishra, Akhil Shrivastava, Ritu Yadav, Pranay Sagar Inst Technol & Sci SIRTS Dept Comp Sci & Engn CSE Bhopal India Sagar Inst Res & Technol SIRT Dept Comp Sci & Engn CSE Bhopal India Maulana Azad Natl Inst Technol MANIT Dept Comp Sci Engn CSE Bhopal India

ISBN: (纸本)9781665483285;9781665483292

The cloud and its applications have been growing rapidly in the last decade, but every coin has two sides: positive and negative. The good thing about that is that online work is growing quickly, but the bad thing is that attacks are becoming more and more powerful. In the current generation, cyber-attacks are one of the most threatening issues for cloud-based applications. Different cloud attacks are presented, in which Denial of Service (DDoS) is one of the perilous attacks that consume the network bandwidth as well as computing resources of a targeted system. Users of the cloud service now have protection against DDoS attacks that are caused by people who haven't been given permission. In order to prevent the D-DoS attack, this research work has presented a modified feature selection approach. The proposed machine learning approach is separated into three parts: training, testing, and validation. The training of the proposed method requires a previous attack dataset. In 2017, the Canadian Institute of Cyber Security presented a data set for D-DoS attacks. This attack contains four categories, which are labelled as "Slowloris," "Slowhttptest," " Hulk," and "Begian.". For weight optimization, the proposed method employs the Levenberg-Marquardt method, and for validation, a cascaded feed-forward neural network is used. It is well known that, the machine learning algorithms consume a huge amount of time to train models. Introducing a fast training for parallel processing model will make it an efficient tool to reduce the time consumed for training process. It has been shown that the presented approach gives an adequate improvement in accuracy, that is, 99.96%.

关键词： D-DoS Attack Cyber-attack Confusion Matrix Cascaded Feed Forward Neural network (CCFFNN) Levenberg-Marquardt Botnets

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Dynamic Heterogeneous Voltage Regulation for Systolic Array-based DNN Accelerators 38

Dynamic Heterogeneous Voltage Regulation for Systolic Array-...

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38th IEEE International conference on Computer Design (ICCD)

作者： Chen, Jianhao Riad, Joseph Sanchez-Sinencio, Edgar Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

ISBN: (纸本)9781728197104

With the growing performance and wide application of deep neural networks (DNNs), recent years have seen enormous efforts on DNN accelerator hardware design for platforms from mobile devices to data centers. The systolic array has been a popular architectural choice for many proposed DNN accelerators with hundreds to thousands of processing elements (PEs) for parallel computing. Systolic array-based DNN accelerators for datacenter applications have high power consumption and non-uniform workload distribution, which makes power delivery network (PDN) design challenging. Server-class multicore processors have benefited from distributed on-chip voltage regulation and heterogeneous voltage regulation (HVR) for improving energy efficiency while guaranteeing power delivery integrity. This paper presents the first work on HVR-based PDN architecture and control for systolic array-based DNN accelerators. We propose to employ a PDN architecture comprising heterogeneous on-chip and off-chip voltage regulators and multiple power domains. By analyzing patterns of typical DNN workloads via a modeling framework, we propose a DNN workload-aware dynamic PDN control policy to maximize system energy efficiency while ensuring power integrity. We demonstrate significant energy efficiency improvements brought by the proposed PDN architecture, dynamic control, and power gating, which lead to a more than five-fold reduction of leakage energy and PDN energy overhead for systolic array DNN accelerators.

关键词： Deep neural networks

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Graph Database based Knowledge Graph Storage and Query for Power Equipment Management 12

Graph Database Based Knowledge Graph Storage and Query for P...

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12th IEEE PES Asia-Pacific Power and Energy Engineering conference, APPEEC 2020

作者： Tang, Yachen Liu, Tingting He, Ming Wang, Qiang Zhang, Huamin Liu, Guangyi Dai, Renchang Geiri North America San JoseCA United States State Grid Sichuan Electric Power Company Chengdu Sichuan China

ISBN: (纸本)9781728157481

The knowledge graph is a graph-based data structure that mines the value of data from a large number of associations. Therefore, it is necessary to find a database that can support the expression, storage, and query of associated data as a way of storing knowledge graph. Different than the normally used relational database and RDF tabular storage, the graph database stores data in 'vertex' and 'edge' as basic storage units, which can realize distributed storage and parallel processing of massive data with complex associations. The graph database utilizes the characteristics of physical 'pointing' between nodes to provide 'no index' association operations for adjacent nodes and has technical advantages in applications of network-structured data. This paper proposes a knowledge graph storage and query method based on the graph database, and compares the storage and query performance between the general storage format of RDF and graph database based on a constructed power equipment management knowledge graph. © 2020 IEEE.

关键词： Graph Databases

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33rd International conference on Architecture of Computing Systems, ARCS 2020

33rd International Conference on Architecture of Computing S...

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33rd International conference on Architecture of Computing Systems, ARCS 2020

ISBN: (纸本)9783030527938

The proceedings contain 18 papers. The special focus in this conference is on Architecture of Computing Systems. The topics include: Engineering an optimized instruction set architecture for amidar processors;scaling logic locking schemes to multi-module hardware designs;exploration of power domain partitioning with concurrent task mapping and scheduling for application-specific multi-core socs;scalable, decentralized battery management system based on self-organizing nodes;security improvements by separating the cryptographic protocol from the network stack onto a multi-mcu architecture;equally distributed bus-communication access rights for inter mcu communication using multimaster spi;on the evaluation of seu effects on axi interconnect within ap-socs;satellite onboard data reduction using a risc-v core inside an rtg4-based data processing pipeline;accelerating real-time applications with predictable work-stealing;evaluating dynamic task scheduling with priorities and adaptive aging in a task-based runtime system;an architecture for solving the eigenvalue problem on embedded fpgas;ECC memory for fault tolerant risc-v processors;3D optimisation of software application mappings on heterogeneous mpsocs;towards a priority-based task distribution strategy for an artificial hormone system;*** db: A concept for parallel data processing on heterogeneous hardware;investigating transactional memory for high performance embedded systems.

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A Graph Partitioning Algorithm for Edge or Vertex Balance 31st

A Graph Partitioning Algorithm for Edge or Vertex Balance

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31st International conference on Database and Expert Systems Applications (DEXA)

作者： El Moussawi, Adnan Seghouani, Nacera Bennacer Bugiotti, Francesca Lab Rech Informat LRI F-91190 Gif Sur Yvette France

ISBN: (纸本)9783030590031;9783030590024

The definition of effective strategies for graph partitioning is a major challenge in distributed environments since an effective graph partitioning allows to considerably improve the performance of large graph data analytics computations. In this paper, we propose a multi-objective and scalable Balanced GRAph Partitioning (B-GRAP) algorithm to produce balanced graph partitions. B-GRAP is based on Label Propagation (LP) approach and defines different objective functions to deal with either vertex or edge balance constraints while considering edge direction in graphs. The experiments are performed on various graphs while varying the number of partitions. We evaluate B-GRAP using several quality measures and the computation time. The results show that B-GRAP (i) provides a good balance while reducing the cuts between the different computed partitions (ii) reduces the global computation time, compared to Spinner algorithm.

关键词： Large graph partitioning Vertex balance Edge balance parallel processing

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In-network processing Acoustic Data for Anomaly Detection in Smart Factory

In-Network Processing Acoustic Data for Anomaly Detection in...

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2021 IEEE Global Communications conference (GLOBECOM)

作者： Huanzhuo Wu Yunbin Shen Xun Xiao Artur Hecker Frank H.P. Fitzek Deutsche Telekom Chair of Communication Networks Technische Universität Dresden Germany Munich Research Center Huawei Technologies Muenchen Germany Centre for Tactile Internet with Human-in-the-Loop (CeTI)

ISBN: (纸本)9781728181059

Modern manufacturing is now deeply integrating new technologies such as 5G, Internet-of-things (IoT), and cloud/edge computing to shape manufacturing to a new level – Smart Factory. Autonomic anomaly detection (e.g., malfunctioning machines and hazard situations) in a factory hall is on the list and expects to be realized with massive IoT sensor deployments. In this paper, we consider acoustic data-based anomaly detection, which is widely used in factories because sound information reflects richer internal states while videos cannot; besides, the capital investment of an audio system is more economically friendly. However, a unique challenge of using audio data is that sounds are mixed when collecting thus source data separation is inevitable. A traditional way transfers audio data all to a centralized point for separation. Nevertheless, such a centralized manner (i.e., data transferring and then analyzing) may delay prompt reactions to critical anomalies. We demonstrate that this job can be transformed into an in-network processing scheme and thus further accelerated. Specifically, we propose a progressive processing scheme where data separation jobs are distributed as microservices on intermediate nodes in parallel with data forwarding. Therefore, collected audio data can be separated 43.75% faster with even less total computing resources. This solution is comprehensively evaluated with numerical simulations, compared with benchmark solutions, and results justify its advantages.

关键词： Shape Microservice architectures distributed databases Numerical simulation Acoustics Production facilities Task analysis

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TATA: Throughput-Aware TAsk Placement in Heterogeneous Stream processing with Deep Reinforcement Learning

TATA: Throughput-Aware TAsk Placement in Heterogeneous Strea...

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IEEE International conference on Big Data and Cloud Computing (BdCloud)

作者： Xiao Huang Yu Jiang Hao Fan Huayun Tang Yiping Wang Jin Jin Hai Wan Xibin Zhao Tsinghua University Beijing China ChinaBond Finance And Information Technology Co. Ltd. Beijing China Maple Growth Research Club Institution Toronto Canada

Data Stream processing (DSP) applications, which generate real-time analytics on continuous data flows, have become prevalent recently. For the deployment of DSP applications, task placement is an important and essential part. As determining the optimal task placement is an NP-hard problem, several efficient heuristics have been designed and Deep Reinforcement Learning (DRL) was used to train the scheduling agent. Current DRL-based approach assumes all resources including CPU, memory and networking are homogeneous. However, the available computation and network resources are heterogeneous in many scenarios. To deal with it, we devise a general DRL-based resource-aware framework, which models resources using graph embedding and attention mechanism to predict the placement. Furthermore, in order to accelerate the training process and improve the throughput, we propose an efficient throughput estimation tool, which can estimate the throughput with high accuracy. We integrated our scheduling heuristic framework into Apache Flink and conducted comprehensive testings using multiple synthetic and real DSP applications. The experimental results show that our framework increases the throughput by 64%, 42%, 29% on average respectively compared with three state-of-the-art strategies.

关键词： Training Processor scheduling NP-hard problem Estimation Reinforcement learning Predictive models Throughput

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SRAM-PUF based Lightweight Mutual Authentication Scheme for IoT

SRAM-PUF Based Lightweight Mutual Authentication Scheme for ...

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IEEE International conference on Big Data and Cloud Computing (BdCloud)

作者： Yongqing Zhu Zhenyu Guan Ziyi Wang Dawei Li Yawei Wang Mai Xu School of Cyber Science and Technology Beihang University Beijing China Beijing Aerospace Changfeng Co. Ltd. Beijing China School of Electronic and Information Engineering Beihang University Beijing China

The Internet of Things (IoT) is essentially a network infrastructure which connects smart devices together. However, IoT endpoint devices are widely deployed in a public and unprotected environment. The devices are facing security issues such as identity forgery and illegal access. Hence, in this paper, we propose a lightweight mutual authentication scheme with physically unclonable function(PUF) running in SRAM, which ensures the authenticity of devices and nodes at a low cost. In addition, this scheme has high security for resisting physical cloning attacks, replay attacks, man-in-the-middle attacks, and spoofing attacks. Furthermore, the device needs no more than two complex algorithms to implement proposed authentication, which means the scheme is easy to deploy. This scheme utilizes a distributed architecture with a central server, which adds no additional pressure on the IoT nodes and centres. In this paper, the scheme is proved to be correct, efficient and suitable for IoT scenarios by a prototype implemented with a MSP430V254IPZR MCU, which is widespread in the IoT nowadays.

关键词： Meters Costs Authentication Cloning Computer architecture Smart meters Servers

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