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Evaluating and Optimizing OpenCL Base64 Data Unpacking Kernel with FPGA 26

Evaluating and Optimizing OpenCL Base64 Data Unpacking Kerne...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Jin, Zheming Johnson, Iris Finkel, Hal Argonne Natl Lab Leadership Comp Facil Argonne IL 60439 USA Northern Illinois Univ Dept Compute Sci De Kalb IL 60115 USA

ISBN: (纸本)9781538649756

Development of applications using OpenCL targeting FPGAs is an emerging approach on heterogeneous computing systems. This paper uses the data unpacking algorithm in Base64 encoding as a case study to present programming and optimization techniques, and experimental results of the OpenCL-based implementations on an FPGA. We explain the algorithm and evaluate the performance of the kernel implementations with Intel's FPGA OpenCL SDK. The experimental results show kernel vectorization and duplication are two optimization techniques that can improve the kernel performance. The performance of kernel duplication is also closely related to the local work size. Our experiment shows 16-lane vectorization increases the bandwidth by a factor of 2 to 10 for large input data sizes. Moreover, the performance of kernel duplication using 16 compute units is 40% to 1.5% less than that of kernel vectorization depending on the input size. Tuning the local work size can improve the kernel performance by a factor of 3 to 23. For this kernel, using local memory is not an effective technique to improve the kernel performance because input data is not reused. A combination of vectorization and duplication achieves the highest performance of 12.3 GiB/s. Compared to an Intel Xeon E5 CPU and an Nvidia Tesla K80 GPU, the performance of the kernel on the Arria 10 FPGA is 6.7X faster than the CPU and 3X slower than the GPU. The performance per watt on the FPGA is 20.5X higher than the CPU and 1.19X lower than the GPU.

关键词： FPGA OpenCL Base64 Encoding

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CSSMT: Compiler based Software Simultaneous Multithreading (SMT) 26

CSSMT: Compiler based Software Simultaneous Multithreading (...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Chen, Yuanfang Shi, Qingchuan Li, Xiaoming Univ Delaware Elect & Comp Engn Dept Newark DE 19716 USA Adv Micro Devices Inc Santa Cruz CA USA

ISBN: (纸本)9781538649756

Simultaneous multithreading (SMT) is a unique computer architecture feature to increase the pipeline utilization and therefore, increase the instruction throughput. It improves instruction level throughput by simultaneously filling both vertical and horizontal super-scalar pipeline slots that are left unfilled by native threads. So far SMT has been implemented in hardware. However, hardware SMT implementations have its limitations. First, it is complex and expensive to implement-only higher-end processors are equipped with it even though lower-end processors have same pipeline design as the higher-end variants and might also benefit from it. SMT also introduces great power/energy and area overheads. Moreover, being a hardware feature, SMT is limited by the range and depth of instruction analysis that it can afford at execution time, therefore it is unlikely to benefit from high-level software knowledge about instruction mix and might lose many improvement opportunities. In this paper, we address the limitation of the hardware-based SMT and introduce CSSMT: Compiler based Software Simultaneous Multithreading (SMT). The main contribution of CSSMT is that it exploits high-level program profiles to purposefully "re-mix" instructions from multiple programs to better fill vertical and horizontal super-scalar pipeline slots so that the overall throughput is improved. Furthermore, CSSMT is a software-transformation technique that enables SMT at software level during compilation time. Therefore, it can help overcome the limitation of the hardware-based SMT implementation and is more portable. We test CSSMT with programs from SPEC2006 and NAS benchmarks and achieve up to 12% speedup of execution time (30.7% improvement in terms of multi-program throughput).

关键词： Compiler LLVM Simultaneous multithreading SMT

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MixedCache: Enabling Flow Directed Rule-Caching Scheme based on Heterogeneous Cache for OpenFlow 3

MixedCache: Enabling Flow Directed Rule-Caching Scheme based...

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2020 3rd International conference on Computer Information Science and Artificial Intelligence, CISAI 2020

作者： Yang, Jialun Yang, Yi Liu, Jiahao Liu, Rulin Qiao, Peng Wang, Baosheng College of Computer Science and Technology National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China

OpenFlow switches in SDN use Multiple Flow Tables (MFTs) for fine-grained flow control. Commodity switches integrate hardware storage resources such as SRAM and TCAM to store flow tables to achieve high-speed lookups. Many increased flow tables are rapidly exhausting these hardware storage resources, which makes the switches have to balance high-speed search and massive storage. The rule-caching scheme is a popular method to solve this problem, which caches the most commonly used rules into hardware storage resources. The existing rule-caching schemes are based on single hardware storage resources, and they cannot flexibly adjust the caching strategy according to the traffic characteristics. Simultaneously, the deployed commodity switches face the problem of difficulty in changing the size of SRAM and TCAM. This paper innovatively proposes the MixedCache scheme, which makes full use of the hardware storage resources in the switch according to the skewed characteristics of network traffic. MixedCache stores the large flows in SRAM by exact match and stores the small flows in the TCAM by wildcard match. MixedCache does not need to change the size of the deployed switch hardware storage resources, but makes full use of existing resources. Compared with the rule-caching scheme based on the exact match, the cache hit rate can increase by up to 15.61%. Compared with the rule-caching scheme based on the wildcard match, the cache hit rate can increase by up to 29.69%. © Published under licence by IOP Publishing Ltd.

关键词： Static random access storage

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Scheduling Placement-Sensitive BSP Jobs with Inaccurate Execution Time Estimation 38

Scheduling Placement-Sensitive BSP Jobs with Inaccurate Exec...

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39th IEEE International conference on Computer Communications (IEEE INFOCOM)

作者： Han, Zhenhua Tan, Haisheng Jiang, Shaofeng H-C Fu, Xiaoming Cao, Wanli Lau, Francis C. M. Univ Sci & Technol China Hefei Anhui Peoples R China Univ Hong Kong Hong Kong Peoples R China Weizmann Inst Sci Rehovot Israel Univ Gottingen Gottingen Germany

ISBN: (数字)9781728164120

ISBN: (纸本)9781728164120

The Bulk Synchronous parallel (BSP) paradigm is gaining tremendous importance recently because of the popularity of computations such as distributed machine learning and graph computation. In a typical BSP job, multiple workers concurrently conduct iterative computations, where frequent synchronization is required. Therefore, the workers should be scheduled simultaneously and their placement on different computing devices could significantly affect the performance. Simply retrofitting a traditional scheduling discipline will likely not yield the desired performance due to the unique characteristics of BSP jobs. In this work, we derive SPIN, a novel scheduling designed for BSP jobs with placement-sensitive execution to minimize the makespan of all jobs. We first prove the problem approximation hardness and then present how SPIN solves it with a rounding-based randomized approximation approach. Our analysis indicates SPIN achieves a good performance guarantee efficiently. Moreover, SPIN is robust against misestimation of job execution time by theoretically bounding its negative impact. We implement SPIN on a production-trace driven testbed with 40 GPUs. Our extensive experiments show that SPIN can reduce the job makespan and the average job completion time by up to 3x and 4.68x, respectively. Our approach also demonstrates better robustness to execution time misestimation compared with heuristic baselines.

关键词： Graphics processing units Servers Processor scheduling Machine learning Robustness Estimation error

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16th IFIP WG 10.3 International conference on network and parallel Computing, NPC 2019

16th IFIP WG 10.3 International Conference on Network and Pa...

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16th IFIP WG 10.3 International conference on network and parallel Computing, NPC 2019

ISBN: (纸本)9783030307080

The proceedings contain 37 papers. The special focus in this conference is on International conference on network and parallel Computing, NPC 2019. The topics include: High Performance DDoS Attack Detection System based on Distribution Statistics;DDP-B: A distributed Dynamic parallel Framework for Meta-genomics Binary Similarity;Optimal Resource Allocation Through Joint VM Selection and Placement in Private Clouds;a parallel Multi-keyword Top-k Search Scheme over Encrypted Cloud Data;N-Docker: A NVM-HDD Hybrid Docker Storage Framework to Improve Docker Performance;MMSR: A Multi-model Super Resolution Framework;HiPower: A High-Performance RDMA Acceleration Solution for distributed Transaction processing;LDAPRoam: A Generic Solution for Both Web-based and Non-Web-based Federate Access;characterizing Perception Module Performance and Robustness in Production-Scale Autonomous Driving System;Game-based Multi-MD with QoS Computation Offloading for Mobile Edge Computing of Limited Computation Capacity;Spindle: A Write-Optimized NVM Cache for Journaling File System;two-Erasure Codes from 3-Plexes;deep Fusion: A Software Scheduling Method for Memory Access Optimization;optimizing Data Placement on Hierarchical Storage Architecture via Machine Learning;i/O Optimizations based on Workload Characteristics for parallel File Systems;Energy Consumption of IT System in Cloud Data Center: Architecture, Factors and Prediction;Efficient processing of Convolutional Neural networks on SW26010;ADMMLIB: A Library of Communication-Efficient AD-ADMM for distributed Machine Learning;energy-Aware Resource Scheduling with Fault-Tolerance in Edge Computing;DIN: A Bio-Inspired distributed Intelligence networking;KLSAT: An Application Mapping Algorithm based on Kernighan–Lin Partition and Simulated Annealing for a Specific WK-Recursive NoC Architecture;A DAG Refactor based Automatic Execution Optimization Mechanism for Spark.

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SharP Data Constructs: Data Constructs to Enable Data-centric Computing 26

SharP Data Constructs: Data Constructs to Enable Data-centri...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Aderholdt, Ferrol Venkata, Manjunath Gorentla Parchman, Zachary W. Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN 37830 USA Tennessee Technol Univ Comp Sci Dept Cookeville TN 38501 USA

ISBN: (纸本)9781538649756

Extreme-scale applications (i.e., Big-Compute) are becoming increasingly data-intensive, i.e., producing and consuming increasingly large amounts of data. The HPC systems traditionally used for these applications are now used for Big-Data applications such as data analytics, social network analysis, machine learning, and genomics. As a consequence of these trends, the system architecture should be flexible and data-centric. This can already be witnessed in the pre-exascale systems with TBs of on-node hierarchical and heterogeneous memories, PBs of system memory, low-latency, high-throughput networks, and many threaded cores. As such, the pre-exascale systems suit the needs of both Big-Compute and Big-Data applications. Though the system architecture is flexible enough to support both Big-Compute and Big-Data, we argue there is a software gap. Particularly, we need data-centric abstractions to leverage the full potential of the system, i.e., there is a need for native support for data resilience, the ability to express data locality and affinity, mechanisms to reduce data movement, the ability to share data, and abstractions to express User's data usage and data access patterns. In this paper, we (i) show the need for taking a holistic approach towards data-centric abstractions, (ii) show how these approaches were realized in the SHARed data-structure centric Programming abstraction (SharP) library, a data-structure centric programming abstraction, and (iii) apply these approaches to a variety of applications that demonstrate its usefulness. Particularly, we apply these approaches to QMCPack and the Graph500 benchmark and demonstrate the advantages of this approach on extreme-scale systems.

关键词： Libraries Data structures Resilience Memory management Benchmark testing distributed databases Random access memory

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Multi-agent Supply Planning Methods Allowing the Real-Time Performance of the Supply network Management Systems 1

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9th International conference on Industrial Applications of Holonic and Multi-Agent Systems (HoloMAS)

作者： Tsarev, Alexander ICCS RAS Samara Russia

ISBN: (数字)9783030278786

ISBN: (纸本)9783030278786;9783030278779

The paper deals with the questions of how to develop the automated planning systems that are fast enough to be used in real-time management of supply networks, considering the manual plan corrections by the users. Several practical situations and planning system use cases are considered. The paper proposes several methods that allow the increase of the data processing speed in practical cases. The methods include parallel data processing, dynamic control of the solutions space depth search, self-regulation of the system behavior based of the specifics of the data processed.

关键词： distributed planning Self-regulation parallel processing Coordination Performance Real-time scheduling Real-time management Multi-agent planning Supply network Supply chain

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Proceedings - 2019 IEEE Intl Conf on parallel and distributed processing with Applications, Big Data and Cloud Computing, Sustainable Computing and Communications, Social Computing and networking, ISPA/BDCloud/SustainCom/SocialCom 2019

Proceedings - 2019 IEEE Intl Conf on Parallel and Distribute...

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17th IEEE International conference on parallel and distributed processing with Applications, 9th IEEE International conference on Big Data and Cloud Computing, 9th IEEE International conference on Sustainable Computing and Communications, 12th IEEE International conference on Social Computing and networking, ISPA/BDCloud/SustainCom/SocialCom 2019

ISBN: (纸本)9781728143286

The proceedings contain 232 papers. The topics discussed include: convolutional neural network-based approach for citrus diseases recognition;using temporal conceptual graphs and neural networks for big data-based attack scenarios reconstruction;taxi demand prediction with LSTM-based combination model;counting attention based on classification confidence for visual question answering;an optimization method of WebP images lossy compression algorithm for FPGAs;self-adaptive address mapping mechanism for access pattern awareness on DRAM;a high-performance self-learning antelopes migration algorithm (SAMA) for global optimization;and using resource use data and system logs for HPC system error propagation and recovery diagnosis.

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Image preprocessing algorithm based on k-means 20

Image preprocessing algorithm based on k-means

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20th International conference on parallel and distributed Computing, Applications and Technologies, PDCAT 2019

作者： Zhao, Xiaofan Cai, Manchun Ren, Yuan Yang, Fan School of Information Technology and Cyber Security People's Public Security University of China Beijing China

ISBN: (纸本)9781728126166

With the development of image acquisition and storage technology, the image data is greatly increased. How to process the increasing image data quickly has become the main problem of image processing. In this paper, the image data are processed by K-means algorithm in Python language environment, and the original image and the image processed by K-means algorithm are classified and trained in convolution neural network. The experimental results show that the time consumed by the image processed by K-means algorithm is 20 s to 30 s less than that of the original image in convolution neural network. It can effectively improve the efficiency of image processing. © 2019 IEEE.

关键词： K-means clustering

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Low Precision Deep Learning Training on Mobile Heterogeneous Platform

Low Precision Deep Learning Training on Mobile Heterogeneous...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Valery, Olivier Liu, Pangfeng Wu, Jan-Jan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781538649756

Recent advances in System-on-Chip architectures have made the use of deep learning suitable for a number of applications on mobile devices. Unfortunately, due to the computational cost of neural network training, it is often limited to inference task, e.g., prediction, on mobile devices. In this paper, we propose a deep learning framework that enables both deep learning training and inference tasks on mobile devices. While being able to accommodate with the heterogeneity of computing devices technology on mobile devices, it also uses OpenCL to efficiently leverage modern SoC capabilities, e.g., multi-core CPU, integrated GPU and shared memory architecture, and accelerate deep learning computation. In addition, our system encodes the arithmetic operations of deep networks down to 8-bit fixed-point on mobile devices. As a proof of concept, we trained three well-known neural networks on mobile devices and exhibited a significant performance gain, energy consumption reduction, and memory saving.

关键词： OpenCL GPGPU mobile computing heterogeneous system System-on-Chip deep learning transfer learning

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